LM3S2965-IQC20-A0T Luminary Micro, Inc., LM3S2965-IQC20-A0T Datasheet - Page 77

• Manufacturer Part Number: LM3S2965-IQC20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

June 04, 2007
Bit/Field
26:23
22
21
20
USEPWMDIV
USESYSDIV
reserved
SYSDIV
Name
Type
R/W
R/W
R/W
RO
Reset
0xF
0
1
0
Preliminary
Description
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
When reading the Run-Mode Clock Configuration (RCC) register (see
page 76), the SYSDIV value is MINSYSDIV if a lower divider was
requested and the PLL is being used. This lower value is allowed to
divide a non-PLL source.
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Use the PWM clock divider as the source for the PWM clock.
Binary Value
0000-0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Divisor (BYPASS=1)
reserved
/8
/10
/12
/14
/16
/18
/20
/22
/24
/26
/28
/30
/32
Frequency (BYPASS=0)
reserved
50 MHz
40 MHz
33.33 MHz
28.57 MHz
25 MHz
22.22 MHz
20 MHz
18.18 MHz
16.67 MHz
15.38 MHz
14.29 MHz
13.33 MHz
12.5 MHz (default)
LM3S2965 Microcontroller
77