LM3S2965-IQC20-A0T Luminary Micro, Inc., LM3S2965-IQC20-A0T Datasheet - Page 219

• Manufacturer Part Number: LM3S2965-IQC20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0x0000.0000
June 04, 2007
Reset
Reset
Type
Type
Bit/Field
31:11
7:4
10
9
8
3
2
RO
RO
31
15
0
0
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
RO
RO
30
14
0
0
reserved
reserved
TBTOIM
CBMIM
CBEIM
RTCIM
CAEIM
reserved
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
R/W
R/W
0
0
RO
RO
CBEIM
R/W
RO
26
10
0
0
Reset
CBMIM
0
0
0
0
0
0
0
R/W
RO
25
0
9
0
Preliminary
TBTOIM
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM CaptureB Event Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
GPTM CaptureB Match Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
GPTM TimerB Time-Out Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM RTC Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
GPTM CaptureA Event Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
R/W
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S2965 Microcontroller
RTCIM
R/W
RO
19
0
3
0
CAEIM
R/W
RO
18
0
2
0
CAMIM
R/W
RO
17
0
1
0
TATOIM
R/W
RO
16
0
0
0
219