LM3S2965-IQC20-A0T Luminary Micro, Inc., LM3S2965-IQC20-A0T Datasheet - Page 341

• Manufacturer Part Number: LM3S2965-IQC20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

14.4
Table 14-1. SSI Register Map
June 04, 2007
Offset
0x00C
0x01C
0x000
0x004
0x008
0x010
0x014
0x018
Name
SSICR0
SSICR1
SSIDR
SSISR
SSICPSR
SSIIM
SSIRIS
SSIMIS
■
■
■
■
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1.
2.
3.
4.
5.
Register Map
“Register Map” on page 341 lists the SSI registers. The offset listed is a hexadecimal increment to
the register’s address, relative to that SSI module’s base address:
■
■
Note:
Master operation
Freescale SPI mode (SPO=1, SPH=1)
1 Mbps bit rate
8 data bits
SSI0: 0x4000.8000
SSI1: 0x4000.9000
Ensure that the SSE bit in the SSICR1 register is disabled.
Write the SSICR1 register with a value of 0x00000000.
Write the SSICPSR register with a value of 0x00000002.
Write the SSICR0 register with a value of 0x000009C7.
The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0003
0x0000.0000
0x0000.0000
0x0000.0008
0x0000.0000
Reset
Preliminary
Description
SSI Control 0
SSI Control 1
SSI Data
SSI Status
SSI Clock Prescale
SSI Interrupt Mask
SSI Raw Interrupt Status
SSI Masked Interrupt Status
LM3S2965 Microcontroller
page
See
343
345
347
348
349
350
351
352
341