LM3S2965-IQC20-A0T Luminary Micro, Inc., LM3S2965-IQC20-A0T Datasheet - Page 279
LM3S2965-IQC20-A0T
Manufacturer Part Number
LM3S2965-IQC20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S2965-IQC20-A0T.pdf
(542 pages)
- Current page: 279 of 542
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ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0)
Base 0x4003.8000
Offset 0x048
Type RO, reset 0x0000.0000
June 04, 2007
Reset
Reset
Type
Type
Bit/Field
31:10
9:0
RO
RO
31
15
0
0
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
This register contains the conversion results for samples collected with the Sample Sequencer (the
ADCSSFIF0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1, and
ADCSSFIFO2 for Sequencer 2). Reads of this register return conversion result data in the order
sample 0, sample 1, and so on, until the FIFO is empty. If the FIFO is not properly handled by
software, overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT
registers.
RO
RO
30
14
0
0
reserved
Name
DATA
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
26
10
0
0
Reset
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Conversion result data.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
DATA
RO
RO
20
0
4
0
LM3S2965 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
279
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