LM3S2965-IQC20-A0T Luminary Micro, Inc., LM3S2965-IQC20-A0T Datasheet - Page 236

• Manufacturer Part Number: LM3S2965-IQC20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Watchdog Timer
11.3
11.4
Table 11-1. Watchdog Timer Register Map
236
Offset
0x00C
0x000
0x004
0x008
0x010
0x014
0x418
Name
WDTLOAD
WDTVALUE
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTTEST
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1.
2.
3.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACCE551.
Register Map
“Register Map” on page 236 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Load the WDTLOAD register with the desired timer load value.
If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
Type
R/W
R/W
R/W
WO
RO
RO
RO
0xFFFF.FFFF
0xFFFF.FFFF
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Reset
-
Preliminary
Description
Watchdog Load
Watchdog Value
Watchdog Control
Watchdog Interrupt Clear
Watchdog Raw Interrupt Status
Watchdog Masked Interrupt Status
Watchdog Test
June 04, 2007
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