LM3S2965-IQC20-A0T Luminary Micro, Inc., LM3S2965-IQC20-A0T Datasheet - Page 454
LM3S2965-IQC20-A0T
Manufacturer Part Number
LM3S2965-IQC20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S2965-IQC20-A0T.pdf
(542 pages)
- Current page: 454 of 542
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Analog Comparators
Analog Comparator Reference Voltage Control (ACREFCTL)
Base 0x4003.C000
Offset 0x10
Type R/W, reset 0x0000.0000
454
Reset
Reset
Type
Type
Bit/Field
31:10
7:4
3:0
9
8
RO
RO
31
15
0
0
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset
0x10
This register specifies whether the resistor ladder is powered on as well as the range and tap.
RO
RO
30
14
0
0
reserved
reserved
Name
VREF
RNG
EN
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
0
0
RO
RO
RO
RO
26
10
0
0
Reset
0
0
0
0
0
R/W
RO
EN
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
The EN bit specifies whether the resistor ladder is powered on. If 0, the
resistor ladder is unpowered. If 1, the resistor ladder is connected to
the analog V
This bit is reset to 0 so that the internal reference consumes the least
amount of power if not used and programmed.
The RNG bit specifies the range of the resistor ladder. If 0, the resistor
ladder has a total resistance of 32 R. If 1, the resistor ladder has a total
resistance of 24 R.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
The VREF bit field specifies the resistor ladder tap that is passed through
an analog multiplexer. The voltage corresponding to the tap position is
the internal reference voltage available for comparison. See Table
17-4 on page 448 for some output reference voltage examples.
RNG
R/W
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
DD
.
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
RO
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
VREF
June 04, 2007
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
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