LM3S2965-IQC20-A0T Luminary Micro, Inc., LM3S2965-IQC20-A0T Datasheet - Page 217

• Manufacturer Part Number: LM3S2965-IQC20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x00C
Type R/W, reset 0x0x0000.0000
June 04, 2007
Reset
Reset
Type
Type
Bit/Field
31:15
11:10
14
13
12
9
reserved
RO
RO
31
15
0
0
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
TBPWML
R/W
RO
30
14
0
0
TBEVENT
TBPWML
TBSTALL
reserved
reserved
TBOTE
Name
TBOTE
R/W
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
R/W
RO
Type
27
11
R/W
R/W
R/W
R/W
0
0
RO
RO
TBEVENT
R/W
RO
26
10
0
0
Reset
TBSTALL
0
0
0
0
0
0
R/W
RO
25
0
9
0
Preliminary
TBEN
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerB PWM Output Level
0: Output is unaffected.
1: Output is inverted.
GPTM TimerB Output Trigger Enable
0: The output TimerB trigger is disabled.
1: The output TimerB trigger is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerB Event Mode
00: Positive edge.
01: Negative edge.
10: Reserved.
11: Both edges.
GPTM TimerB Stall Enable
0: TimerB stalling is disabled.
1: TimerB stalling is enabled.
R/W
RO
24
0
8
0
reserved
reserved
RO
RO
23
0
7
0
TAPWML
R/W
RO
22
0
6
0
TAOTE
R/W
RO
21
0
5
0
RTCEN
R/W
RO
20
0
4
0
LM3S2965 Microcontroller
R/W
RO
19
0
3
0
TAEVENT
R/W
RO
18
0
2
0
TASTALL
R/W
RO
17
0
1
0
TAEN
R/W
RO
16
0
0
0
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