LM3S2965-IQC20-A0T Luminary Micro, Inc., LM3S2965-IQC20-A0T Datasheet - Page 87

• Manufacturer Part Number: LM3S2965-IQC20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO
June 04, 2007
Reset
Reset
Type
Type
Bit/Field
31:26
23:21
19:17
15:12
11:8
25
24
20
16
7
RO
RO
31
15
0
0
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. The PWM, SARADC0,
MAXADCSPD, WDT, SWO, SWD, and JTAG bits mask the RCGC0, SCGC0, and DCGC0 registers.
Other bits are passed as 0. MAXADCSPD is clipped to the maximum value specified in DC1.
RO
RO
30
14
0
0
MAXADCSPD
SYSDIV
SARADC0
reserved
reserved
reserved
SYSDIV
Name
CAN1
CAN0
PWM
MPU
RO
RO
29
13
0
1
reserved
RO
RO
28
12
0
1
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
MAXADCSPD
RO
26
10
0
0
Reset
0x3
0x3
0
1
1
0
1
0
1
1
CAN1
RO
RO
25
1
9
1
Preliminary
CAN0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, indicates that CAN unit 1 is present.
When set, indicates that CAN unit 0 is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, indicates that the PWM module is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, indicates that general SAR ADC 0 is present.
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
This field indicates the maximum rate at which the ADC samples data.
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
RO
RO
Value
0x3
Value
0x3
24
1
8
1
Description
Specifies a 50-MHz CPU clock with a PLL divider of 4.
Description
1M samples/second
MPU
RO
RO
23
0
7
1
reserved
HIB
RO
RO
22
0
6
1
TEMPSNS
RO
RO
21
0
5
1
PWM
PLL
RO
RO
20
1
4
1
LM3S2965 Microcontroller
WDT
RO
RO
19
0
3
1
reserved
SWO
RO
RO
18
0
2
1
SWD
RO
RO
17
0
1
1
SARADC0
JTAG
RO
RO
16
1
0
1
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