LM3S2965-IQC20-A0T Luminary Micro, Inc., LM3S2965-IQC20-A0T Datasheet - Page 282

• Manufacturer Part Number: LM3S2965-IQC20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Analog-to-Digital Converter (ADC)
ADC Sample Sequence Control 1 (ADCSSCTL1)
Base 0x4003.8000
Offset 0x064
Type R/W, reset 0x0000.0000
282
Reset
Reset
Type
Type
Bit/Field
31:16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TS3
R/W
RO
31
15
0
0
Register 20: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 1. When configuring a sample sequence, the END bit must be set at some point,
whether it be after the first sample, last sample, or any sample in between. This register is 16-bits
wide and contains information for four possible samples.
R/W
RO
IE3
30
14
0
0
reserved
Name
END3
END2
END1
END0
TS3
TS2
TS1
TS0
END3
IE3
IE2
IE1
IE0
R/W
D3
D2
D1
D0
RO
29
13
0
0
R/W
RO
28
12
D3
0
0
TS2
R/W
RO
Type
27
11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
RO
R/W
RO
IE2
26
10
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
END2
R/W
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Same definition as TS7 but used during the fourth sample.
Same definition as IE7 but used during the fourth sample.
Same definition as END7 but used during the fourth sample.
Same definition as D7 but used during the fourth sample.
Same definition as TS7 but used during the third sample.
Same definition as IE7 but used during the third sample.
Same definition as END7 but used during the third sample.
Same definition as D7 but used during the third sample.
Same definition as TS7 but used during the second sample.
Same definition as IE7 but used during the second sample.
Same definition as END7 but used during the second sample.
Same definition as D7 but used during the second sample.
Same definition as TS7 but used during the first sample.
Same definition as IE7 but used during the first sample.
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
Same definition as D7 but used during the first sample.
R/W
RO
D2
24
0
8
0
reserved
R/W
TS1
RO
23
0
7
0
R/W
RO
IE1
22
0
6
0
END1
R/W
RO
21
0
5
0
R/W
RO
D1
20
0
4
0
R/W
TS0
RO
19
0
3
0
R/W
RO
IE0
18
0
2
0
June 04, 2007
END0
R/W
RO
17
0
1
0
R/W
RO
D0
16
0
0
0