LM3S2965-IQC20-A0T Luminary Micro, Inc., LM3S2965-IQC20-A0T Datasheet - Page 457

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LM3S2965-IQC20-A0T

Manufacturer Part Number
LM3S2965-IQC20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
June 04, 2007
Bit/Field
6:5
3:2
4
1
0
reserved
ISLVAL
Name
TSEN
CINV
ISEN
Type
R/W
R/W
R/W
R/W
RO
Reset
0
0
0
0
0
Preliminary
Description
The TSEN field specifies the sense of the comparator output that
generates an ADC event. The sense conditioning is as follows:
The ISLVAL bit specifies the sense value of the input that generates
an interrupt if in Level Sense mode. If 0, an interrupt is generated if the
comparator output is Low. Otherwise, an interrupt is generated if the
comparator output is High.
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
The CINV bit conditionally inverts the output of the comparator. If 0, the
output of the comparator is unchanged. If 1, the output of the comparator
is inverted prior to being processed by hardware.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
TSEN
00
01
10
11
ISEN
00
01
10
11
Function
Level sense, see ISLVAL
Falling edge
Rising edge
Either edge
Function
Level sense, see TSLVAL
Falling edge
Rising edge
Either edge
LM3S2965 Microcontroller
457

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