MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 121

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MT9072

Manufacturer Part Number
MT9072
Description
Octal T1-E1-J1 Framer
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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Advance Information
15-10
9-8
7-0
Bit
RXLDCM
RXLDCL
Name
(0000
0001)
(00)
1-0
7-0
#
Table 79 - Receive Loop Deactivate code Match Register (R/W Address YF0)
not used
Receive Loop Deactivate Code Length. These 2 bits define the length of the receive loop up
code.
00-Code length is 5 bits
01-Code length is 6 or 3 bits
10-Code length is 7 bits
11-Code length is 8 or 4 bits
Note: if 3 bit code or 4 bit code is required the bits have to be repeated in RXLACM7-0. For
instance if the code 1011 is desired the RXLACM has to be set to 10111011 and the RXLACL to
11. In case of the 3 bit code the 2 most significant bits of RXLACM are ignored.
Receive Loop Deactivate Code Match.This byte specifies the match code for the receive
loopback activate code. A maskable interrupt can be generated if the loopback activate code
message is received. This byte is compared to RXLAC.
The default values are the T1.403 values for Loop Activate Code.
Functional Description
MT9072
121

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