MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 60

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
Frame Alignment Signal (NFAS) frame. Data for DL transmission should be written to DSTi immediately
following the NFAS frame (during FAS frames) and before the start of the next NFAS frame.
The ST-BUS Data Link (DL) access is enabled if the Sa Source Select Bits (Sa4SS-SA8SS) are set to ’10’ in
register Y08. ST-BUS DSTi timeslot 0 bits will be transmitted as NFAS bits on the PCM30 link, as shown in
Table 19 (bit positions one to eight of timeslot zero, of odd CRC-4 frames 1, 3, 5, 7, 9, 11, 13, 15).
The DL data received on the PCM30 link is always output to ST-BUS DSTo timeslot 0 during NFAS frames,
regardless of the settings of SA4SS to SA8SS.
6.2.4
Non-Frame Alignment Signal (NFAS) bits on the receive PCM30 link (bit positions one to eight of timeslot 0 of
odd CRC-4 frames 1, 3, 5, 7, 9, 11, 13, 15) are sourced to the ST-BUS DSTo stream.The data to DSTo is
mapped unaltered from the receive PCM30 link as shown in Table 20.
6.3
Bit Oriented Messages can be sent on the FDL in ESF mode.
Bit - Oriented Messages may be transmitted via the TxBOM register (Y07) and received in the RxBOM (Y12).
Transmission is enabled by setting bit 2 - BOMEn in the HDLC &Data link Control Word(Y06). Bit - oriented
messages may be periodically interrupted (up to once per second) for a duration of up to 100 milliseconds. This
is to accommodate bursts of message - oriented protocols. Table 21 shows the messages that can be sent and
received according to T1.403. The transmit data link will contain the repeating serial data stream
111111110xxxxxx0 where the byte 0xxxxxx0 originates from the user programmed register “Transmit Bit
Oriented Message” - Y07. The receive BOM register “Receive Bit Oriented Message” - Y12, will contain the last
received valid message (the 0xxxxxx0 portion of the incoming serial bit stream). To prevent spurious inputs
from creating false messages, a new message must be present in 8 of the last 10 appropriate byte positions
before being loaded into the receive BOM register. When a new message has been received, a maskable
interrupt (maskable by setting bit 4 low in Receive Line status and Timer Mask (Y45) may occur. Bit oriented
messages are only applicable in the ESF mode.
60
All NFAS
Note 1. For 2.048Mbit/s operation, n=0.
Note 2. For 8.192Mbit/s operation, n =0,1,2,3 where n corresponds to the framer number (i.e. n=0=framer 0... n=3= framer 3).
Note 3. For these functions to be valid, NFAS DSTi ST-BUS mode access must be enabled (SA4SS to SA8SS register address Y08).
Note 4. For these functions to be valid, the Timeslot Control Registers must be disabled (all bits=0 register address Y90-YAF).
All NFAS
Note 1. For 2.048Mbit/s operation, n=0.
Note 2. For 8.192Mbit/s operation, n =0,1,2,3 where n corresponds to the framer number (i.e. n=0=framer 0... n=3= framer 3).
Note 3. To source the NFAS, Sa bits from DSTi, ST-BUS mode access must be enabled (SA4SS to SA8SS = 10 register address
CRC-4
Frame
CRC-4
Frame
Table 19 - Transmit PCM30 National Bits from ST-BUS 2.048Mbit/s or 8.192Mbit/s DSTi (E1)
T1 Bit Oriented Message
Table 20 - Receive PCM30 National Bits to ST-BUS 2.048Mbit/s or 8.192Mbit/s DSTo (E1)
Y08.
E1 Timeslot 0 CRC-4 NFAS Receive from PCM30 to DSTo
n
Timeslot
n
Timeslot
ST-BUS DSTo
ST-BUS DSTi
P1, P2, P3, Sa4, Sa5, Sa6,
Sa7, Sa8
P1, P2, P3, Sa4, Sa5, Sa6,
Sa7, Sa8
Data Bits (B7-B0)
Data Bits (B7-B0)
0
0
Timeslot
Timeslot
All NFAS
All NFAS
CRC-4
CRC-4
Frame
Frame
PCM30 Transmit
PCM30 Receive
P1, P2, P3, Sa4, Sa5, Sa6,
Sa7, Sa8
P1, P2, P3, Sa4, Sa5, Sa6,
Sa7, Sa8
Advance Information
Data Bits (B1-B8)
Data Bits (B1-B8)