MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 18

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
Pin Description (continued)
18
LQFP
130
155
115
35
55
75
16
96
Pin #
LBGA
M15
G13
C15
T14
G2
T1
T7
L3
DSTo[1]
DSTo[2]
DSTo[3]
DSTo[5]
DSTo[6]
DSTo[7]
CSTi[0]
CSTi[4]
Name
Type
O
I
Data ST-BUS. In 2.048Mbit/s ST-BUS mode and IMA mode this pin is
an output for the receive side of the framer. This pin is not used in
8.192Mbit/s ST-BUS mode. Pins DSTo[0-7] are used by Framers[0-7]
respectively.
In T1 mode, this pin outputs 2.048Mbit/s ST-BUS data. The first 24
channels contain the 24 8-bit channels received on the PCM24
interface. Channel 31 bit 0 contains the received S-bit in D4 and ESF
modes. See Table 1.The DSTo data stream is clocked out of the
framer by the clock input to pin CKi. The DSTo pin is enabled if the
DSToEN control bit (Address YF1) is set to 1.
In T1 IMA mode, this pin outputs the 1.544Mbit/s received serial
stream. The serial stream contains the framing bit followed by the 24
8-bit channels received on the PCM24 interface. See Table 3. In IMA
mode the DSTo data stream is clocked out of the framer by the clock
output by the RxDLC pin. The DSto pin is enabled if the DSToEN
control bit (Address YF1) is set to 1. IMA mode is selected by setting
the IMA bit (Address Y00) to 1.
In E1 mode, this pin outputs 2.048Mbit/s ST-BUS data. The 32
channels contain the 32 channels of data received on the PCM30
interface. See Table 4 and Table 6. The DSTo data stream is clocked
out of the framer by the clock input to pin CKi. The DSTo pin is
enabled if the DSToE control bit (Address Y02) is set to 1.
In E1 IMA mode, this pin outputs the 2.048Mbit/s received serial
stream. See Table 4 and Table 6. In IMA mode the DSTo data stream
is clocked out of the framer by the clock output by the RxDLC pin. The
DSTo pin is enabled if the DSToE control bit (Address Y02) is set to 1.
IMA mode is selected by setting the IMA bit (Address Y00) to 1.
Control ST-BUS. This pin is the signaling input for the transmit side of
the framer. In 2.048 Mbit/s ST-BUS mode it operates the same as
CSTi(1-3), it can also operate in 8.192Mbit/s ST-BUS mode. The CSTi
data stream is clocked into the framer by the clock input to pin CKi.
This pin has no function in IMA mode.
When operated in 8.192Mbit/s ST-BUS mode this pin accepts a data
stream containing 128 8-bit channels accommodating four framers.
See Table 2 and Table 5. The frame boundary is indicated by the FPi
inputs. Pin CSTi[0] is used by Framers[0-3] and pin CSTi[4] is used by
Framers[4-7].
The 32 ST-BUS channels mapped to each framer are treated as
described for CSTi(1-3) operating at 2.048Mbit/s.
Description (see Notes 1 to 7)
Advance Information