MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 147

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MT9072

Manufacturer Part Number
MT9072
Description
Octal T1-E1-J1 Framer
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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Advance Information
15-8
Bit
7-0
(00000000)
TxSD7-0
Name
#
not used.
Transmit Set Delay Bits 7 - 0. Writing to this register forces a one time setting of the delay
through the transmit slip buffer. The binary value written to the Transmit Set Delay Bits
defines the delay between the write of the Transmit ST-BUS Channel containing DS1
timeslot 1 (first timeslot) and its read from the slip buffer.
If the value written to the Transmit Set Delay Bits is 00H to BFH then the delay can be
calculated as: (Value) / (1.544 x 10
If the value written to the Transmit Set Delay Bits is C0H to FFH then the delay can be
calculated as: (255 - value) / (2.048 x 10
After a reset there will be an immediate transmit slip and the subsequent delay through the
transmit slip buffer will be one frame.
Table 122 - TX Set Delay Bits (YF7) (T1)
Functional Description
6
) seconds.
6
) seconds.
MT9072
147

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