MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 73

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
The least significant bit of the Transmit FIFO data is sent first on the serial stream.
Frame aborts (the transmission of 7F hex), are transmitted by tagging a byte previously written to the Tx FIFO.
When a byte has an FA tag, then an FA is sent instead of that tagged byte. That is, all bytes previous to but not
including that byte are sent. After a Frame Abort, the transmitter returns to the Mark Idle or Interframe Time Fill
state, depending on the state of the Mark idle control bit.
Tx FIFO underrun will occur if the FIFO empties and the last byte did not have either an EOP or FA tag. A
frame abort sequence will be sent when an underrun occurs.
Below is an example of the transmission of a three byte packet (’AA’ ’03’ ’77’ hex) (Interframe time fill). TXcen
can be enabled before or after this sequence.
The transmitter may be enabled independently of the receiver. This is done by setting the TXEN bit of the
Control Register YF2. Enabling happens immediately upon writing to the register. Disabling using TXen will
occur after the completion of the transmission of the present packet; the contents of the FIFO are not cleared.
Disabling will consist of stopping the transmitter clock. The Status and Interrupt Registers may still be read and
the FIFO and Control Registers may be written to while the transmitter is disabled. The transmitted FCS may
be inhibited using the Tcrci bit of HDLC Master Control Register. In this mode the opening flag followed by the
data and closing flag is sent and zero insertion still included, but no CRC. That is, the FCS is injected by the
microprocessor as part of the data field. This is used in V.120 terminal adaptation for synchronous protocol
sensitive UI frames.
8.1.9
After initialization and enabling, the receiver clocks in serial data, continuously checking for Go-aheads (0 1111
1110), flags (0111 1110), and Idle Channel states (at least fifteen ones). When a flag is detected, the receiver
synchronizes itself to the serial stream of data bits, automatically calculating the FCS. If the data length
between flags after zero removal is less than 25 bits, then the packet is ignored so no bytes are loaded into Rx
FIFO. When the data length after zero removal is between 25 and 31 bits, a first byte and bad FCS code are
loaded into the Rx FIFO (see definition of RQ8 and RQ9 below).
If address recognition is required, the Receiver Address Recognition Registers are loaded with the desired
address and the Adrec bit in the HDLC Control Register is set high(YF2). Bit 0 and 8 of the Address Register
are used as enable bits for their respective byte, thus allowing either or both of the first two bytes to be
compared to the expected values. Bit 0 of the first byte of the address received (address extension bit) will be
monitored to determine if a single or dual byte address is being received. If this bit is 0 then a two byte address
is being received and then only the first six bits of the first address byte are compared. An all call condition is
also monitored for the second address byte; and if received the first address byte is ignored (not compared with
mask byte). If the address extension bit is a 1 then a single byte address is being received. In this case, an all
call condition is monitored for in the first byte as well as the mask byte written to the comparison register and
the second byte is ignored. Seven bits of address comparison can be realized on the first byte if this is a single
byte address by setting the Seven bit of HDLC control register(YF2).
T
FIFO. They indicate that a good packet has been received (good FCS and no frame abort), or a bad packet
with either incorrect FCS or frame abort. The Status and Interrupt Registers should be read before reading the
Rx FIFO since Status and Interrupt information correspond to the byte at the output of the FIFO (i.e. the byte
about to be read). The Status Register bits are encoded as follow
he following two Status Register bits (RQ8 and RQ9) are appended to each data byte as it is written to the Rx
HDLC Receiver
(a) Write’0020’hex to Control Register 1
(b) Write’AA’ hex to TX FIFO
(c) Write’03’hex to TX FIFO
(d) Write’01A0’ hex to Control Register 1
(e) Write’77’hex to TX FIFO
RQ9
1
0
RQ8
1
1
last byte (bad packet)
Byte status
first byte
-Mark idle bit set
-Data byte
-Data byte
-TXEN; EOP; Mark idle bits set
-Final data byte
s:
MT9072
73