MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 58

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
6.2.1
The pin (TxDL, TxDLC, RxDL and RxDLC) enable bits Sa4SS to Sa8SS of control register address Y08
determine the type of data link access enabled. A ’01’ code enables the corresponding data link (DL) bits to be
sourced to and from the RxDL and TxDL pins, by enabling the corresponding pulses in either gapped clocks or
enable low signals provided at the RxDLC and TxDLC pins. The option of either gapped clock or enable signal
is selected by control bit DLCK (register address Y08). The data link bits are transmitted on and received from
the PCM30 link, in the national bit (Sa4 to Sa8) positions (four to eight of timeslot zero) of the Non-Frame
Alignment Signal (NFAS) frames. The gapped clock rate will be either 4, 8, 12, 16 or 20kb/s, and will depend on
the number of Sa bits enabled by SA#SS bits (register Y08). Similarly the enable pulse width(s) will also
depend on the number of Sa bits enabled.
6.2.1.1 E1 Data Link (DL) Pin Data Transmitted on PCM30
Data to be transmitted onto the line in the S
Although the aggregate clock rate equals the bit rate, it has a nominal pulse width of 244 ns, and it clocks in the
TxDL as if it were a 2.048Mbit/s data stream. The clock can only be active during bit times 4 to 0 of the ST-BUS
frame. The TxDL input signal is clocked into the MT9072 by the falling edge of TxDLC which occurs about 3/4
into the ST-BUS bit cell. If DL bits are selected to be accessed through the DL pins, then all other programmed
functions for those S
6.2.1.2 E1 Data Link (DL) Pin Data Received on PCM30 - With No Elastic Buffer
The RxDLC clock and enable signal is derived from the receive extracted clock (EXCLi) and is aligned with the
receive data link output RxDL. The HDB3 decoded receive data, at 2.048Mbit/s, is clocked out of the device on
the RxDL pin with the falling edge of EXCLi. In order to facilitate the attachment of this data stream to a Data
Link controller, the clock signal RxDLC consists of positive pulses, of nominal width of 244 ns, during the S
cell times that are selected for the data link, with the rising edge aligned with the middle of the bit cell. No DL
data will be lost or repeated when a receive frame slip occurs as the DL data does not pass through the elastic
buffer. The output signal at the RxDLC pin may be either a clock or an enable signal as programmed by the
DLCK control bit (register address Y08). See Figures 62 & 63 for timing requirements.
58
YC0-YC4 Receive national bit
Register
Address
YB0-YB4 Transmit National Bits
Y00
Y06
Y08
Y13
Y26
Y36
Y46
E1 Data Link (DL) Pin Access
Alarm and Framing Control
Register
HDLC and CCS ST-BUS
control register
Data Link Control Register
NFAS and FAS status
CAS, National, CRC-4
Latched Status
CAS, National, CRC-4
Interrupt Status
CAS, National, CRC-4
Interrupt Mask
Table 17 - Data Link and Sa bits Configuration and Status Registers (E1)
a
bit positions are overridden. See Figures 59 & 60 for timing requirements.
Register
The Data Link is not supported in the IMA mode.
The bit HPSEL has to be 0 if the internal HDLC is to be used for the
Data Link.
This register determines the source of the Sa bits which can be micro
port,HDLC, data link pins or ST-BUS. This register is also used to
control the data link pins Txdl and Rxdl.
The national use bits RNU can be read from this status register.
The Sa bit latched values can be read from this register, SA5VL,
SA6NL etc.
The Sa bit interrupt values can be read from this register, SA5VI,
SA6NI etc.
These are the mask bits for Y36.
Transmit national bits used for sending
Sa bits(SA4 to SA8).
Receive National bits(SA4 to SA8)
a
bit position is clocked in from the TxDL pin with the TxDLC clock.
Description
Advance Information
a
bit