MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 201

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
16.2.7
Tables 125 and 126 describe the bit functions of the Interrupt Vector Masks, while tables 186 to 189 describe
the bit functions of each of the Interrupt Mask Registers in the MT9072. Each interrupt mask register is
repeated for each of the 8 framers (not the Interrupt Vector Masks). Framer 0 is addressed with Y=0, Framer 1
with Y=1, Framer 2 with Y=2 and so on up to Framer 7 with Y=7 (where Y represents the 4 most significant
address bits (MSB) A11-A8). In addition, a simultaneous write to all 8 framers is possible by setting the MSB
address to Y=8 (1000). However, since the Interrupt Vector Masks are common to all eight framers, only
addresses 902 and 903 may be used to read from or write to these registers.
A (0), (1) or (#) in the “Name” column of these tables indicates the state of the data bits after a reset (RESET,
RSTC or RST). The (#) indicates that a (0) or (1) is possible.
15-9
Bit
8
7
6
5
4
3
2
1
0
Interrupt Vector Mask and Interrupt Mask Registers (Y4X) Bit Functions
TXUNDERIM
RXOVFLIM
EOPDIM
EOPRIM
TEOPIM
RXFFIM
TXFLIM
Name
GAIM
FAIM
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
#
Table 186 - HDLC Interrupt Mask Register (Address Y43) (E1)
not used.
GAIM When unmasked an interrupt is generated when go-ahead pattern (01111111)
was detected by the HDLC receiver.
End of Packet Data Interrupt Mask.When unmasked an interrupt is initiated when an
end of packet (EOP) byte was written into the RX FIFO by the HDLC receiver.
Transmit End of Packet Interrupt Mask.When unmasked an interrupt is initiated
when the byte about to be read from the RX FIFO is the last byte of the packet. An
interrupt is also initiated if the Rx FIFO is read and there is no data in it.
End of Packet Received Interrupt Mask.When unmasked an interrupt is initiated
when the byte about to be read from the RX FIFO is the last byte of the packet. An
interrupt is also initiated if the Rx FIFO is read and there is no data in it.
Transmit Fifo Low Interrupt Mask.When unmasked an interrupt is initiated when the
Tx FIFO is emptied below the selected low threshold level.
Transmit Elastic Buffer full interrupt Mask. When unmasked an interrupt is initiated
whenever the transmit elastic buffer is full.If 1 - masked, 0 - unmasked.
Transmit Fifo Underrun Interrupt Mask. interrupt is initiated for TX FIFO underrun
indication.
Receive Fifo full Threshold interrupt Mask. When unmasked an interrupt is initiated
whenever the Rx FIFO is filled above the selected full threshold level.
Receive Fifo Overflow Interrupt Mask. When unmasked an interrupt is initiated
whenever the 16 byte RX FIFO overflowed (i.e. an attempt to write to a 16 byte full RX
FIFO).
Functional Description
MT9072
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