MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 3

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Data Link
One Embedded Floating HDLC per Framer
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1. TxDL and RxDL pins support transmit and
2. Bit Oriented Messages are supported via
3. An internal HDLC can be assigned to transmit/
Flag generation and Frame Check Sequence (FCS) generation and detection, zero insertion and
deletion
Continuous flags, or continuous 1s are transmitted between frames
Transmit frame-abort
Invalid frame handling:
Access is provided to the receive FCS
FCS generation can be inhibited for terminal adaptation
Recognizes single byte, dual byte and all call addresses
Independent, 32 byte deep transmit and receive FIFOs
Receive FIFO maskable interrupts for nearly full and overflow conditions
Transmit FIFO maskable interrupts for nearly empty and underflow conditions
Maskable interrupts for transmit end-of–packet and receive end-of-packet
Maskable interrupts for receive bad-frame (includes frame abort)
Transmit-to-receive and receive-to-transmit loopbacks are provided
Transmit and receive bit rates and enables are independent
Frame aborts can be sent under software control and they are automatically transmitted in the event of
a transmit FIFO underrun
Three methods are provided to access the
datalink:
Assignable to the ESF Facility Data Link or
any other channel
Operates at 4 kbit/s (FDL), 56 kbit/s or
receive datalinks
internal registers
receive over the FDL in ESF mode
64 kbit/s
Frames yielding an incorrect FCS are tagged as bad packets
Frames with fewer than 25 bits are ignored
Frames with fewer than 32 bits between flags are tagged as bad packets
Frames interrupted by a Frame-Abort sequence remain in the FIFO and an interrupt is generated
T1/J1 Mode
T1/J1 Mode
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1. TxDL and RxDL pins support transmit and
2. An internal HDLC can be assigned to transmit/
Two methods are provided to access the
datalink:
In transparent mode, if the Sa4 bit is used for
an intermediate datalink, the CRC-4
remainder can be updated to reflect changes
to the Sa4 bit
Assignable to timeslot-0, bits Sa4~Sa8 or
any other timeslot
Operates at 4, 8, 12, 16 or 20 kbit/s (Sa bits)
or 64 kbit/s
receive datalinks over the Sa4~Sa8 bits
receive data via the Sa4~Sa8 bits
E1 Mode
E1 Mode
MT9072
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