MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 216

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
216
Bit
15
14
13
12
11
10
9
8
7
6
5
Name
F3HM
F3EM
F3RM
F3SM
F2HM
F2EM
F2RM
F2SM
F1HM
F1EM
F1RM
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Framer 3 HDLC Mask. This is the mask bit for the F3HVS status bit in the Interrupt Vector
Register(address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 3 Elastic Mask. This is the mask bit for the F3EVS status bit in the Interrupt Vector
Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 3 Rx Line Mask. This is the mask bit for the F3RVS status bit in the Interrupt Vector
Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 3 Sync and Overflow Mask. This is the mask bit for the F3SVS status bit in the Interrupt
Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit
will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 2 HDLC Mask. This is the mask bit for the F2HVS status bit in the Interrupt Vector
Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 2 Elastic Mask. This is the mask bit for the F2EVS status bit in the Interrupt Vector
Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 2 Rx Line Mask. This is the mask bit for the F2RVS status bit in the Interrupt Vector
Register(address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 2 Sync and Overflow Mask. This is the mask bit for the F2SVS status bit in the Interrupt
Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit
will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 1 HDLC Mask. This is the mask bit for the F1HVS status bit in the Interrupt Vector
Register(address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 1 Elastic Mask. This is the mask bit for the F1EVS status bit in the Interrupt Vector
Register(address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Framer 1 Rx Line Mask. This is the mask bit for the F1RVS status bit in the Interrupt Vector
Register(address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Table 201 - Interrupt Vector 1 Mask Register (R/W Address 902) (E1)
Functional Description
Advance Information