MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 89

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
13.1.7
The per channel conditioning capabilities of MT9072 are explained in this section. For the receiver the T1 data
can be replaced by the conditioning data (Y09) via the bit MPDR in the per channel control registers(Y90 to
YA7).
This data will be output to the corresponding DSTo channel. The received data can be inverted on a per
channel basis by setting the RPCI bit (register Y90 to YA7). The transmit data can be inverted on a per channel
basis with a write to the control bit TPCI (registers Y90 to YA7). The transmit data can also be frozen on a per
channel basis; in this case the data from the DSTI is not used to update the Transmit Memory and the data
written in Y0A is used as the source (MPDT in registers Y90 to YA7).
13.2 E1 Maintenance and Alarms
Extensive maintenance and alarm generation and detection functions are provided on the MT9072. The
following table groups the registers for control and monitor of these functions.
Transmit ESF Yellow Alarm. Setting this bit (while in ESF mode)
causes a repeating pattern of eight 1’s followed by eight 0’s to be
insert onto the transmit FDL.
Transmit Secondary D4 Yellow Alarm. Setting this bit (in D4
mode) causes the S-bit of transmit frame 12 to be set.
Transmit All Ones. When low, this control bit forces a framed or
unframed (depending on the state of Transmit Alarm Control bit 0)
all ones to be transmit at TTIP and TRING
S-bit Override. If set, this bit forces the S-bits to be inserted as an
overlay on any of the following alarm conditions: i) transmit all ones,
ii) loop up code insertion, iii) loop down code insertion.
TT1DMY. If reset to low a yellow alarm is sent in the 24th channel if
the T1DM option is set.
Register
Address
Y00
Y01
Y05
Y10
Y12
Y11
T1 Per Timeslot Trunk Conditioning
Alarm and Framing Control Register The TAIS and E bit errors and RAI can be set by this register.
Test Error and Loopback Control
Register
CAS Control and Data Register
Synchronization and CRC-4
Remote Status
CRC-4 Timer and CRC-4 Local
Status
Alarms and MAS Status
Table 47 - Registers Related to Maintenance and Alarms (E1)
Register
Description
Table 46 - Alarm Control and Status Bits (T1)
Control/Status Register
BPVE, CRCE,FASE, NFSE and E bit errors can be inserted.
The Y bit can be used to send Remote Multiframe Alarm signal.
The bits of this register provide good receiver error status.
The CRC-4 errors are registered in Y11.
This register provides AIS, RAI, LOSS status bits.
TESFYEL
TT1DMY
TSECY
TAIS
SO
Bit
Description
Address
Y02
Y02
Y02
Y02
Y02
Interrupt Status
Bit
NA
NA
NA
NA
NA
Register
MT9072
Address
NA
NA
NA
NA
NA
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