MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 212

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
16.2.13
Tables 194 to 197 describe the bit functions of each of the Master Control Registers in the MT9072 in E1
Mode(YF0 to YF6). Each register is repeated for each of the 8 framers. Framer 0 is addressed with Y=0,
Framer 1 with Y=1, Framer 2 with Y=2 and so on up to Framer 7 with Y=7 (where Y represents the 4 most
significant address bits (MSB) A11-A8). In addition, a simultaneous write to all 8 framers is possible by setting
the MSB address to Y=8 (1000).
A (0), (1) or (#) in the “Name” column of these tables indicates the state of the data bits after a reset (RESET,
RSTC or RST). The (#) indicates that a (0) or (1) is possible.
212
15-11
Bit
10
9
8
7
6
5
4
3
2
1
0
Master Control Registers (YF0 - YF6) Bit Functions
RXFRST
TXFRST
ADREC
SEVEN
CYCLE
TCRCI
RXEN
Name
TXEN
EOP
(0)
(0)
(0)
(0)
FA
(0)
(0)
(0)
(0)
(0)
(0)
(0)
MI
#
not used.
Address Recognition. When high, this bit will enable address recognition. This forces
the receiver to recognize only those packets having the unique address as programmed
in the Receive Address Recognition Registers or if the address is an All Call Address.
Receive Enable. When low this bit will disable the HDLC receiver. The receiver will
disable after the rest of the packet presently being received is finished. The receiver’s
internal clock is disabled.
When high the receiver will be immediately enabled (depending on the state of RXCEN
input) and will begin searching for flags, Go-aheads etc.
Transmit Enable. When low this bit will disable the HDLC transmitter. The transmitter
will disable after the completion of the packet presently being transmitted. The
transmitter’s internal clock is disabled.
When high the transmitter will be immediately enabled (depending on the state of the
TXCEN input) and will begin transmitting data, or go to a mark idle or interframe time fill
state.
End of Packet When set this bit will indicate an end of packet byte to the transmitter,
which will transmit an FCS following this byte. This facilitates loading of multiple packets
into TX FIFO. Reset automatically after a write to the TX FIFO occurs.
Framer Abort.Forms a tag on the next byte written to the TX FIFO, and when set will
indicate to the transmitter that it should abort the packet in which that byte is being
transmitted. Reset automatically after a write to the TX FIFO.
Mark-Idle.When low, the transmitter will be in an idle state. When high it is in an
interframe time fill state. These two states will only occur when the TX FIFO is empty.
Cycle.When high, this bit will cause the transmit byte count to cycle through the value
loaded into the Transmit Byte Count Register.
Transmit CRC Inhibit. When high, this bit will inhibit transmission of the CRC. That is,
the transmitter will not insert the computed CRC onto the bit stream after seeing the EOP
tag byte. This is used in V.120 terminal adaptation for synchronous protocol sensitive UI
frames.
Seven. When high, this bit will enable seven bits of address recognition in the first
address byte. The received address byte must have bit 0 equal to 1 which indicates a
single address byte is being received.
Rx Fifo Reset. When high, the RX FIFO will be reset. This causes the receiver to be
disabled until the next reception of a flag. The status register will identify the FIFO as
being empty. However, the actual bit values in the RX FIFO will not be reset.
Transmit FIFO Reset. When high, the TX FIFO will be reset. The Status Register will
identify the FIFO as being empty. This bit will be reset when data is written to the TX
FIFO. However, the actual bit values of data in the TX FIFO will not be reset.
Table 195 - HDLC Control1(YF2) (E1)
Functional Description
Advance Information