MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 70

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
8.0
The MT9072 has 1 embedded HDLC controller for each of the framers. Each controller may be attached to any
timeslot. The HDLC can also be connected to the FDL bits (T1 ESF Mode) for provision of a 4 Kbit/s Data Link
or Sa bits in E1 mode for data link up to 20Kb/s.
The features of the HDLC are:
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The relevant registers associated with HDLC are listed in Table 32.
8.1
The HDLC handles the bit oriented protocol structure as per layer 2 of the switching protocol X.25 defined by
CCITT. It transmits and receives the packetized data serially while providing data transparency by zero
insertion and deletion. It generates and detects the flags, various link channel states and abort sequences.
Further, it provides a cyclic redundancy check on the data packets using the CCITT defined polynomial. In
addition, it can recognize a single byte, dual byte and all call address in the received frame. Access to Rx CRC
70
Register
Address
Independent transmit and receive FIFO;
Receive FIFO maskable interrupts for nearly full and overflow conditions;
Transmit FIFO maskable interrupts for nearly empty and underflow conditions;
Maskable interrupts for transmit end-of-packet and receive end-of-packet;
Maskable interrupts for receive bad-frame (includes frame abort);
Transmit end-of-packet and frame-abort functions.
Y1D
Y1E
Y06
YF2
YF3
YF4
YF5
YF6
Y1F
Y23
Y33
Y43
HDLC Description
HDLC
HDLC and DataLink Control
HDLC Control
HDLC Test Control
Address Recognition
Transmit FIFO
Transmit Byte Counter
HDLC Status
Receive CRC
Receive FIFO
HDLC Latch Status
HDLC Interrupt Status
HDLC Interrupt Mask
Register
Table 32 - HDLC Related Registers
The bits of this register determine whether the HDLC is connected
to the Data Link or payload.
General configuration for the HDLC.
Control bits for testing the HDLC such as loopbacks.
Address recognition register for storing data in the Receive FIFO of
a packet that matches the received address.
This register is used for writing data to the HDLC Transmit FIFO.
The data from the FIFO can be subsequently sent to Data Link or a
selected channel.
This counter determines the size of the HDLC packet to be sent
when the cycle bit is set(YF2).
This register provides status on the FIFO’s.
This register provides the received FCS of a packet.
This register has to be read to obtain the receive FIFO data.
These register bits are the latched version of the HDLC status.
This register provides the interrupt status of events such as
underflow, go ahead packet etc.
These register bits can be used to mask HDLC events to cause
interrupts.
Description
Advance Information