MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 74

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
The end-of-packet-detect (EOPD) interrupt indicates that the last byte written to the Rx FIFO was an EOP byte
(last byte in a packet). The end-of-packet-read (EOPR) interrupt indicates that the byte about to be read from
the Rx FIFO is an EOP byte (last byte in a packet). The Status Register should be read to see if the packet is
good or bad before the byte is read.
A minimum size packet has an 8-bit address, an 8-bit control byte, and a 16-bit FCS pattern between the
opening and closing flags. Thus, the absence of a data transmission error and a frame length of at least 32 bits
results in the receiver writing a valid packet code with the EOP byte into Rx FIFO. The last 16 bits before the
closing flag are regarded as the FCS pattern and will not be transferred to the receiver FIFO. Only data bytes
(Address, Control, Information) are loaded into the Rx FIFO.
In the case of an Rx FIFO overflow, no clocking occurs until a new opening flag is received. In other words, the
remainder of the packet is not clocked into the FIFO. Also, the top byte of the FIFO will not be written over. If
the FIFO is read before the reception of the next packet then reception of that packet will occur. If two
beginning of packet conditions (RQ9=0;RQ8=1) are seen in the FIFO, without an intermediate EOP status,
then overflow occurred for the first packet.
The receiver may be enabled independently of the transmitter. This is done by setting the RXEN bit of HDLC
Control Register. Enabling happens immediately upon writing to the register. Disabling using RXEN will occur
after the present packet has been completely loaded into the FIFO. Disabling can occur during a packet if no
bytes have been written to the FIFO yet. Disabling will consist of disabling the internal receive clock. The FIFO,
Status, and Interrupt Registers may still be read while the receiver is disabled. Note that the receiver requires a
flag before processing a frame, thus if the receiver is enabled in the middle of an incoming packet it will ignore
that packet and wait for the next complete one.
The receive CRC can be monitored in the Rx CRC Register(Y1E). This register contains the actual CRC sent
by the other transmitter in its original form; that is, MSB first and bits inverted. These registers are updated at
each end of packet (closing flag) received and therefore should be read when an end of packet is received so
that the next packet does not overwrite the registers.
9.0
9.1
The control and status of the MT9072 is achieved through a non-multiplexed parallel microprocessor port
capable of accommodating 12 address bits and 16 data bits. The parallel port may be configured for Motorola
style control signals (by setting pin I/M low) or Intel style control signals (by setting pin I/M high).
9.1.1
The controlling microprocessor gains access to specific registers and framers in the MT9072 through a single
step process. Each of the eight internal framers is identified by the upper four address bits (A11-A8).
Addresses 0XX, 1XX, 2XX... 7XX (where X indicates any hex number between 0 and F) access framers 0,1,2...
7 respectively. Address 8XX accesses all 8 framers simultaneously for processor writes. In addition, there are
seven registers which are global to all eight framers; the Interrupt Vector and the Interrupt Vector Mask
Registers, ST-BUS Select Register and ST-BUS analyzer control registers. These are accessed with
addresses 900 to 911. Throughout this document, the upper four address bits (A11-A8) are referred to as Y,
(where Y indicates any hex number between 0 and 7).
Each register in the eight internal framers is identified by the lower eight address bits (A7-A0). All registers
provided in each of the eight framers are identical, with identical lower eight bit addresses. The lower eight
address bits are partitioned such that the upper four bits (A7-A4) identify the register group (i.e. Control, Status,
Interrupt Mask etc.) and the lower four bits (A3-A0 identify the particular register in the register group (i.e. Tx
Alarm Control Word,signaling Control Word etc.), see Table 34.
74
Processor Interface (A11-A0, D15-D0, I/M, DS, R/W, CS, IRQ, Pins)
MT9072 Access and Control
Framer and Register Access
1
0
0
0
last byte (good packet)
packet byte
Advance Information