MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 65

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
7.2.2
The CSIG control bit (register address Y03) must be set to zero for Channel Associated signaling (CAS)
operation.
Access to the ABCD transmit and receive bits may be either through ST-BUS channels 1 to 15 and channels 17
to 31 at the CSTi and CSTo pins, or through the Transmit CAS Data registers (Y51-Y6F) and Receive CAS
Data registers (Y71-Y8F) accessed by the parallel processor port, or through a mix of both methods. The
timeslot control register bits (CASS(n) address Y90-YAF) determine the source of the CAS data on a per
channel basis. A zero enables an ST-BUS source and a one enables a register source. Note that when
changing the CASS(n) control bits from ST-BUS source to register source on the fly (during normal operation
as opposed to during power up), the data in the Transmit CAS Data registers (Y51-Y6F) should be updated one
frame after the timeslot control register bits (CASS(n)) are changed. This is because the timeslot control
register bits do not take effect immediately. Both destinations of CAS data are always enabled (i.e. ST-BUS
CSTo and receive data registers). ST-BUS CSTi and CSTo channels 0 and 16 are not used.
When the CASRI interrupt is unmasked, IRQ will become active when a signaling state change is detected in
any of the 30 receive channels and a selectable 2 msec, 8 msec or 16 msec timer(Y04 bit 0,1) has expired.
This function helps to reduce the frequency of interrupts generated due to signaling changes. For instance if 7
channels had a signaling change only
interrupt the user has to read the CAS registers(Y70 to Y8F)to determine the channels with a signaling
change.The CASRIM interrupt mask is located in register Y46 bit 4 (clear to enable interrupt); and the CASRI
interrupt status bit in register is Y36 bit 4. Any channels marked as clear channels will not generate an interrupt
due to changes in ABCD bits.
MAS - Multiframe Alignment Signal
NMAS - Non-multiframe Alignment Signal
X - Spare Bit = 1 if not used
Y - Remote Multiframe Alarm Signal
E1 Channel Associated Signaling (CAS) Register and ST-BUS Access
multiframing)
(not related
Associated
Multiframe
to CRC-4
Table 24 - Channel Associated Signaling (CAS) Multiframe Structure (E1)
signaling
Channel
(CAS)
one interrupt will be generated in a 2,8 or 16 msec duration. Upon an
Frame
CAS
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
1
ABCD (ch 10 = ts 10)
ABCD (ch 12 = ts 12)
ABCD (ch 13 = ts 13)
ABCD (ch 14 = ts 14)
ABCD (ch 15 = ts 15)
ABCD (ch 11 = ts 11)
ABCD (ch 2 = ts 2)
ABCD (ch 3 = ts 3)
ABCD (ch 4 = ts 4)
ABCD (ch 5 = ts 5)
ABCD (ch 6 = ts 6)
ABCD (ch 7 = ts 7)
ABCD (ch 8 = ts 8)
ABCD (ch 9 = ts 9)
ABCD (ch 1 = ts1)
0000 (MAS)
2
3
PCM30 Timeslot 16
4
5
ABCD (ch 16 = ts 17)
ABCD (ch 17 = ts 18)
ABCD (ch 18 = ts 19)
ABCD (ch 19 = ts 20)
ABCD (ch 20 = ts 21)
ABCD (ch 21 = ts 22)
ABCD (ch 22 = ts 23)
ABCD (ch 23 = ts 24)
ABCD (ch 24 = ts 25)
ABCD (ch 25 = ts 26)
ABCD (ch 26 = ts 27)
ABCD (ch 27 = ts 28)
ABCD (ch 28 = ts 29)
ABCD (ch 29 = ts 30)
ABCD (ch 30 = ts 31)
XYXX (NMAS)
6
MT9072
7
8
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