MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 31

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Table 54 -JTAG MT9072 Identification Register ................................................................................................. 101
Table 55 -JTAG Boundary-Scan Register ........................................................................................................... 102
16.0 MT9072 Register Set ................................................................................................... 103
Table 56 -Framer Addressing (0XX - 9XX) (T1) .................................................................................................. 103
Table 57 -Register Group Address (Y00 - YFF) Summary (T1) .......................................................................... 104
Table 58 -Global Control and Status (900 - 91F) Summary (T1) ........................................................................ 105
Table 59 - Master Control Registers Address (Y00 to Y0F and YF0 to YFF) Summary (T1).............................. 106
Table 60 -Master Status Register(R) Address(Y1X) Summary (T1) ................................................................... 108
Table 61 -Latched Status Register (R) Address (Y2X) Summary (T1)................................................................ 109
Table 62 -Interrupt Status Register (R) Address (Y3X) Summary (T1) ............................................................... 110
Table 63 -Interrupt Mask Register (R/W) Address (Y4X) Summary (T1) ............................................................ 111
Table 64 -Framing Mode Select (R/W Address Y00) (T1)................................................................................... 112
Table 65 - Line Interface and Coding Word(Y01) (T1) ........................................................................................ 114
Table 66 - Transmit Alarm Control Word(Y02) (T1) ............................................................................................ 115
Table 67 -Transmit Error Control Word(Y03) (T1) ............................................................................................... 115
Table 68 -Signaling Control Word (Y04) (T1) ...................................................................................................... 116
Table 69 -LoopBack Control Word (Y05) (T1)..................................................................................................... 117
Table 70 - HDLC & DataLink Control Word(Y06) (T1) ........................................................................................ 118
Table 71 -Transmit Bit Oriented Message Register (Y07) (T1) ........................................................................... 118
Table 72 -Receive Bit Oriented Message Match Register(Y08) (T1) .................................................................. 119
Table 73 -Receive Idle Code Register(Y09) (T1) ................................................................................................ 119
Table 74 -Transmit Idle Code Register(Y0A) (T1)............................................................................................... 119
Table 75 -Common Channel Signaling Map Register(Y0B) (T1) ........................................................................ 119
Table 76 -Transmit Loop Activate Code Register(Y0D) (T1)............................................................................... 120
Table 77 -Transmit Loop Deactivate Code Register(Y0E) (T1)........................................................................... 120
Table 78 -Receive Loop Activate Code Match Register(Y0F) (T1) ..................................................................... 121
Table 79 -Receive Loop Deactivate code Match Register (R/W Address YF0) .................................................. 121
15.4 JTAG Data Registers ........................................................................................................................... 101
15.5 Boundary Scan Description Language (BSDL) File ............................................................................. 102
16.1 T1 Register Set .................................................................................................................................... 103
15.4.1 Identification Register .................................................................................................................... 101
15.4.2 The Bypass Register ..................................................................................................................... 102
16.1.1 Register Address (000 - FFF) Summaries..................................................................................... 103
16.1.2
16.1.3 Master Status Registers(Y10-Y18)Bit Functions ........................................................................... 122
16.1.1.1.................................................................................... Framer Address (0XX-9XX) Summary 103
16.1.1.2......................................................................Register Group Address (Y00 - YFF) Summary 104
16.1.1.3........................................................Global Control and Status Register (900-91F) Summary 105
16.1.1.4.................................... Master Control Registers Address (Y00-Y0F, YF0 to YFF) Summary 106
16.1.1.5.......................................................... Master Status Registers Address (Y10-Y1F) Summary 108
16.1.1.6........................................................ Latched Status Registers Address (Y20-Y2F) Summary 109
16.1.1.7....................................................... Interrupt Status Registers Address (Y30-Y3F) Summary 110
16.1.1.8......................................................... Interrupt Mask Registers Address (Y40-Y4F) Summary 111
Master Control Registers (Y00 to YF0 ) Bit Functions .................................................................. 112
Table of Contents (continued)
MT9072
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