MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 33

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Table 121 -TX Byte Count Register(YF6) (T1) .................................................................................................... 146
Table 122 -TX Set Delay Bits (YF7) (T1)............................................................................................................. 147
Table 123 -Global Control0 Register (R/W Address 900) (T1) ............................................................................ 148
Table 124 -Global Control1 Register (R/W Address 901) (T1) ............................................................................ 148
Table 125 -Interrupt Vector 1 Mask Register (Address 902) (T1) ....................................................................... 149
Table 126 -Interrupt Vector 2 Mask Register (Address 903) (T1) ....................................................................... 150
Table 127 -Framer Loopback Global Register(904) (T1) .................................................................................... 152
Table 128 -ST-Bus Interrupt Vector Mask(905) (T1) ........................................................................................... 152
Table 129 -Interrupt Vector 1 Status Register (Address 910) (T1) ...................................................................... 153
Table 130 -Interrupt Vector 2 Status Register (Address 911) (T1) ...................................................................... 154
Table 131 -Identification Revision Code Data Register (Address 912) (T1)........................................................ 155
Table 132 -ST-BUS Analyzer Vector Status Register (Address 913) (T1) .......................................................... 155
Table 133 -ST-BUS Analyser Data(Address 920-93F) (T1) ................................................................................ 155
Table 134 -Framer Addressing (000 - FFF) (E1) ................................................................................................. 156
Table 135 -Register Group Address (Y00 - YFF) Summary (E1) ........................................................................ 157
Table 136 -Register Group Address (Y00 - YFF) Summary (E1) ........................................................................ 158
Table 137 -Master Control Register (R/W) Address (Y0X) Summary (E1) ......................................................... 159
Table 138 -Master Status Register (R) Address (Y1X) Summary (E1) ............................................................... 160
Table 139 -Latched Status Register (R) Address (Y2X) Summary (E1) ............................................................. 161
Table 140 -Interrupt Status Register (R) Address Summary (E1) ....................................................................... 162
Table 141 -Interrupt Mask Register (R/W) Address Summary (E1) .................................................................... 163
Table 142 -Transmit CAS Data Register (R/W) Address (Y5X,Y6X) Summary (E1) .......................................... 164
Table 143 -Receive CAS Data Register (R) Address (Y7X,Y8X) Summary (E1)................................................ 165
Table 144 -Timeslot 0-31 Control Register (R/W) Address (Y9X, YAX) Summary (E1) ..................................... 166
Table 145 -Transmit National Bits Data Registers (R/W) Address (YFX) Summary (E1) ................................... 168
Table 146 -Transmit National Bits Data Registers (R/W) Address (YFX) Summary (E1) ................................... 168
Table 147 -Alarm and Framing Control Register Y00 (R/W Address Y00) (E1).................................................. 169
Table 148 -Test, Error and Loopback Control Register (R/W Address Y01) (E1) ............................................... 171
16.2 E1 Register Set .................................................................................................................................... 156
16.1.9 Global Control and Status Registers (900 - 91F) Bit Functions..................................................... 148
16.2.1 Register Address (000 - FFF) Summaries..................................................................................... 156
16.2.2 Register Address (Y00 - YFF) Summary....................................................................................... 159
16.2.3 Master Control Registers (Y00 - Y09) Bit Functions...................................................................... 169
16.2.1.1..................................................................................... Framer Address (000-FFF) Summary 156
16.2.1.2......................................................................Register Group Address (Y00 - YFF) Summary 157
16.2.1.3........................................................Global Control and Status Register (900-91F) Summary 158
16.2.2.1........................................ Master Control Registers Address (Y00-Y0F, YF0-YFF) Summary 159
16.2.2.2.......................................................... Master Status Registers Address (Y10-Y1F) Summary 160
16.2.2.3........................................................ Latched Status Registers Address (Y20-Y2F) Summary 161
16.2.2.4................................................................ Interrupt Status Registers Address Summary(Y3X) 162
16.2.2.5................................................................. Interrupt Mask Registers Address Summary(Y4X) 163
16.2.2.6................................................. Transmit CAS Data Registers Address (Y50-Y6F) Summary 164
16.2.2.7.................................................. Receive CAS Data Registers Address (Y70-Y8F) Summary 165
16.2.2.8............................................. Timeslot 0-31 Control Registers Address (Y90-YAF) Summary 166
16.2.2.9........................... Transmit National Bit Data Register(R/W) Address(YB0 to YB4) Summary 168
16.2.2.10..........................Receive National Bit Data Register(R/W) Address(YC0 to YC4) Summary 168
Table of Contents (continued)
MT9072
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