peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 126

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

periods. This center function of DCO-R can be optionally disabled (CMR2.DCF = 1) in
order to accept a gapped reference clock.
In analog line interface mode the RCLK is always running. Only in digital line interface
mode with single-rail data (NRZ) a gapped clock on pin RCLK can occur.
The receive jitter attenuator works in two different modes:
• Slave mode
• Master mode
The following table shows the clock modes with the corresponding synchronization
sources.
Table 28
Mode
Master
Master
Master
Master
Slave
Slave
Data Sheet
In slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the recovered route
clock. In case of LOS the DCO-R switches automatically to master mode. If bit
CMR1.DCS is set automatic switching from RCLK to SYNC is disabled.
In master mode (LIM0.MAS = 1) the jitter attenuator is in free running mode if no clock
is supplied on pin SYNC. If an external clock on the SYNC input is applied, the DCO-
R synchronizes to this input. The external frequency can be 1.544 MHz
(LIM1.DCOC = 0; IPC.SSYF = 0), 2.048 MHz (LIM1.DCOC = 1; IPC.SSYF = 0) or 8.0
kHz (IPC.SSYF = 1; LIM1.DCOC = don’t care).
Internal
LOS Active
independent Fixed to
independent 1.544 MHz Synchronized on SYNC input (external
independent 2.048 MHz Synchronized on SYNC input (external
independent 8.0 kHz
no
no
System Clocking (T1/J1)
SYNC
Input
V
Fixed to
V
1.544 or
2.048 MHz
DD
DD
System Clocks
DCO-R centered, if CMR2.DCF = 0.
(CMR2.DCF should not be set)
1.544 MHz, IPC.SSYF = 0, LIM1.DCOC = 0)
2.048 MHz, IPC.SSYF = 0, LIM1.DCOC = 1)
Synchronized on SYNC input (external 8.0 kHz,
IPC.SSYF = 1, CMR2.DCF = 0)
Synchronized on line RCLK
Synchronized on line RCLK
126
Functional Description T1/J1
FALC56 V1.2
PEB 2256
2002-08-27