peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 56

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

interrupt source register. After reading the assigned interrupt status registers ISR(5:0),
the pointer in register GIS is cleared or updated if another interrupt requires service.
If all pending interrupts are acknowledged by reading (GIS is reset), pin INT goes
inactive.
Updating of interrupt status registers ISR(5:0) and GIS is only prohibited during read
access.
Masked Interrupts Visible in Status Registers
• The Global Interrupt Status register (GIS) indicates those interrupt status registers
• An additional mode can be selected via bit GCR.VIS.
• In this mode, masked interrupt status bits neither generate an interrupt on pin INT nor
This mode is useful when some interrupt status bits are to be polled in the individual
interrupt status registers.
Note: In the visible mode, all active interrupt status bits, whether the corresponding
Note: All unmasked interrupt statuses are treated as before.
Please note that whenever polling is used, all interrupt status registers concerned have
to be polled individually (no “hierarchical” polling possible), since GIS only contains
information on actually generated, i.e. unmasked interrupts.
Data Sheet
with active interrupt indications (GIS.ISR(5:0)).
are they visible in GIS, but are displayed in the corresponding interrupt status
register(s) ISR(5:0).
actual interrupt is masked or not, are reset when the interrupt status register is
read. Thus, when polling of some interrupt status bits is desired, care must be
taken that unmasked interrupts are not lost in the process.
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Functional Description E1/T1/J1
FALC56 V1.2
PEB 2256
2002-08-27