peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 70

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

4.1.12
The following functions are performed:
• Synchronization on pulse frame and multiframe
• Error indication when synchronization is lost. In this case, AIS is sent automatically to
• Initiating and controlling of resynchronization after reaching the asynchronous state.
• Detection of remote alarm indication from the incoming data stream.
• Separation of service bits and data link bits. This information is stored in status
• Generation of various maskable interrupt statuses of the receiver functions.
• Generation of control signals to synchronize the CRC checker, and the receive elastic
If programmed and applicable to the selected multiframe format, CRC checking of the
incoming data stream is done by generating check bits for a CRC submultiframe
according to the CRC4 procedure (refer to ITU-T G.704). These bits are compared with
those check bits that are received during the next CRC submultiframe. If there is at least
one mismatch, the CRC error counter (16 bit) is incremented.
4.1.13
The received bit stream is stored in the receive elastic buffer. The memory is organized
as a two-frame elastic buffer with a maximum size of 64 × 8 bit. The size of the elastic
buffer can be configured independently for the receive and transmit direction.
Programming of the receive buffer size is done by SIC1.RBS1/0:
• RBS1/0 = 00: two frame buffer or 512 bits
• RBS1/0 = 01: one frame buffer or 256 bits
• RBS1/0 = 10: short buffer or 96 bits
• RBS1/0 = 11: Bypass of the receive elastic buffer
The functions are:
• Clock adaption between system clock (SCLKR) and internally generated route clock
• Compensation of input wander and jitter.
Data Sheet
the system side and remote alarm is sent to the remote end if enabled.
This can be done automatically by the FALC56 or user controlled using the
microprocessor interface.
registers.
buffer.
Maximum of wander amplitude (peak-to-peak): 190 UI (1 UI = 488 ns)
average delay after performing a slip: 1 frame or 256 bits
Maximum of wander amplitude: 100 UI
average delay after performing a slip: 128 bits, (SYPR = output)
Maximum of wander amplitude: 38 UI
average delay after performing a slip: 48 bits, (SYPR = output)
(RCLK).
Framer/Synchronizer (E1)
Receive Elastic Buffer (E1)
70
Functional Description E1
FALC56 V1.2
PEB 2256
2002-08-27