peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 395

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

AFX
CR
EPR
Mode Register 2 (Read/Write)
Value after reset: 00
MODE2
MDS2(2:0)
Data Sheet
MDS22
7
MDS21
Automatic FISU Transmission - HDLC Channel 1
After the contents of the transmit FIFO (XFIFO) has been transmitted
completely, FISUs are transmitted automatically. These FISUs
contain the FSN and BSO of the last transmitted signaling unit
(provided in XFIFO).
0 =
1 =
Command Response - HDLC Channel 1
Reflects the status of the CR bit in the SAPI octet transmitted during
Periodical Performance Report (PPR), if CCR5.EPR = 1.
0 =
1 =
Enable Periodical Performance Report (PPR) - HDLC Channel 1
If the periodical performance report is to be used, an HDLC format
must be selected by MODE.MDS(2:0).
0 =
1 =
Mode Select - HDLC Channel 2
The operating mode of the HDLC controller is selected.
000 = Reserved
001 = Reserved
010 = One-byte address comparison mode (RAL1, 2)
011 = Two-byte address comparison mode (RAH1, 2 and RAL1, 2)
100 = No address comparison
101 = One-byte address comparison mode (RAH1, 2)
110 = Reserved
111 = No HDLC framing mode 1
H
PPR disabled.
PPR enabled.
Automatic FISU transmission disabled.
Automatic FISU transmission enabled.
CR bit = 0
CR bit = 1
MDS20
395
HRAC2
DIV2
T1/J1 Registers
FALC56 V1.2
0
PEB 2256
2002-08-27
(8E)