peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 152

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

• Automatic clock source switching
• Automatic freeze signaling:
5.3.3
The FALC56 offers six error counters where each of them has a length of 16 bit. They
record code violations, framing bit errors, CRC6 bit errors, errored blocks and the
number of received multiframes in asynchronous state or the changes of frame
alignment (COFA). Counting of the multiframes in asynchronous state and of the COFA
parameter is done in a 6/2-bit counter. Each of the error counters is buffered. Buffer
update is done in two modes:
• One-second accumulation
• On demand using handshake with writing to the DEC register.
In the one-second mode an internal/external one-second timer updates these buffers
and resets the counter to accumulate the error events in the next one-second period.
The error counter cannot overflow. Error events occurring during error counter reset are
not be lost.
5.3.4
The FALC56 supports the error performance monitoring by detecting the following
alarms or error events in the received data:
framing errors, CRC errors, code violations, loss of frame alignment, loss-of-signal,
alarm indication signal, receive and transmit slips.
With a programmable interrupt mask register ESM all these alarms or error events can
generate an Errored Second Interrupt (ISR3.ES) if enabled.
5.3.5
Additionally a one-second timer interrupt can be generated internally to indicate that the
enabled alarm status bits or the error counters have to be checked. The one-second
timer signal is output on port SEC/FSC (GPC1.CSFP1/0). Optionally synchronization to
an external second timer is possible which has to be provided on pin SEC/FSC.
Selecting the external second timer is done with GCR.SES. Refer also to register GPC1
for input/output selection.
Data Sheet
In slave mode (LIM0.MAS = 0) the DCO-R synchronizes on the recovered route clock.
In case of loss-of-signal (LOS) the DCO-R switches to master mode automatically. If
bit CMR1.DCS is set, automatic switching from RCLK to SYNC is disabled.
Updating of the received signaling information is controlled by the freeze signaling
status. The freeze signaling status is activated automatically, if a loss-of-signal or a
loss of multiframe alignment or a receive slip occurs. The internal signaling buffer
RS(12:1) is frozen. Optionally automatic freeze signaling is disabled by setting bit
SIC3.DAF = 1.
Error Counter
Errored Second
One-Second Timer
152
Functional Description T1/J1
FALC56 V1.2
PEB 2256
2002-08-27