peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 194

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

7
7.1
The FALC56 can be operated in two principle modes, which are either E1 mode or T1/
J1 mode.
The device is programmable via a microprocessor interface which enables byte or word
access to all control and status registers.
After reset the FALC56 must be initialized first. General guidelines for initialization are
described in
The status registers are read-only and are updated continuously. Normally, the
processor reads the status registers periodically to analyze the alarm status and
signaling data.
7.2
The FALC56 is forced to the reset state if a low signal is input on pin RES for a minimum
period of 10 µs. During reset the FALC56 needs an active clock on pin MCLK. All output
stages are in a high-impedance state, all internal flip-flops are reset and most of the
control registers are initialized with default values.
SIgnals (for example RL1/2 receive line) should not be applied before the device is
powered up.
After reset the device is initialized to E1 operation.
7.3
After reset, the FALC56 is initialized for E1 doubleframe format. To initialize T1/J1 mode,
bit FMR1.PMOD has to be set high. After the internal clocking is settled to T1/J1mode
(takes up to 20 µs), the following register values are initialized :
.
Table 52
Register
FMR0
FMR1
FMR2
Data Sheet
Operational Description T1/J1
Operational Overview T1/J1
Device Reset T1/J1
Device Initialization in T1/J1 Mode
Chapter 7.3
Initial Values after reset and FMR1.PMOD = 1 (T1/J1)
Initiated
Value
00
00
00
H
H
H
Meaning
NRZ coding, no alarm simulation
PCM24 mode, 2.048 Mbit/s system data rate, no AIS
transmission to remote end or system interface, payload
loop off, channel translation mode 0
194
Operational Description T1/J1
FALC56 V1.2
PEB 2256
2002-08-27