peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 204

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

8.1.6
The frames can be transmitted as shown below.
Figure 77
Transmitting a HDLC frame via register CMDR.XTF (or CMDR2.XTF2/CMDR3.XTF3 for
channel 2/3), the address, the control fields and the data field have to be entered in the
XFIFO (XFIFO2, XFIFO3).
If CCR2.XCRC (or CCR3.XCRC2/CCR4.XCRC3 for channel 2/3) is set, the CRC
checksum will not be generated internally. The checksum has to be provided via the
transmit FIFO (XFIFO, XFIFO2, XFIFO3) as the last two bytes. The transmitted frame is
closed automatically with a closing flag only.
The FALC56 does not check whether the length of the frame, i.e. the number of bytes to
be transmitted makes sense or not.
8.2
Characteristics: fully transparent
In no HDLC mode, fully transparent data transmission/reception without HDLC framing
is performed, i.e. without flag generation/recognition, CRC generation/check, or bit
stuffing. This feature can be profitably used e.g. for:
• Specific protocol variations
• Transmission of a BOM frame (channel 1 only)
• Test purposes
Data transmission is always performed out of the XFIFO (XFIFO2, XFIFO3). In
transparent mode, the receive data is shifted into the RFIFO (RFIFO2, RFIFO3).
Note: If a 1-byte frame is sent in extended transparent mode, in addition to interrupt
Data Sheet
Transmit
HDLC
Frame
(XHF)
ISR1.XPR (transmit pool ready) the interrupt ISR1.XDU (transmit buffer underrun)
is set and XFIFO is blocked.
Transmit Data Flow
Extended Transparent Mode
HDLC Transmit Data Flow
FLAG
ADDRESS
ADDR
XFIFO
CONTROL
CTRL
204
Signaling Controller Operating Modes
Ι
DATA
CHECKRAM
CRC
FALC56 V1.2
ITD06456
PEB 2256
FLAG
2002-08-27