peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 178

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

FS/DL data on system transmit highway (XDI), time slot 0:
Figure 69
5.5.2.1
The pulse length of SYPR and RFM is always the basic T1/J1 bit width (648 ns) in 1.544-
MHz mode or the E1 bit width (488 ns) in 2.048-MHz mode.
This chapter describes the system highway operation in 1.544-MHz mode only. If the
system highway is operated in 2.048-MHz mode, the description given in
Chapter 4.5.2.1
SYPX Offset Calculation
T:
BF:
SC:
X:
0 ≤ T ≤ 4:
5 ≤ T ≤ T
Data Sheet
Time between the active edge of SCLKX after SYPX pulse begin and beginning
of the next frame (F-bit, channel phase 0), measured in number of SCLKX clock
intervals; maximum delay: T
Basic frequency; 1.544 Mbit/s
System clock rate; 1.544, 3.088, 6.176, or 12.352 MHz
Programming value to be written to registers RC0 and RC1 (see
max
Transmit Offset Programming
: X = (200 × SC/BF) - T + 3
Transmit FS/DL Bits on XDI (T1/J1)
X = 3 - T + (7 × SC/BF)
on
page 111
MSB
1
2
applies.
3
max
FS/DL Time-Slot
= (200 × SC/BF) - (7 × SC/BF) - 1
4
178
5
6
Functional Description T1/J1
7
FS/DL
LSB
8
FS/DL Data Bit
ITD06460
FALC56 V1.2
page
PEB 2256
2002-08-27
356).