peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 388

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peb2256

Manufacturer Part Number
peb2256
Description
E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet

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Port Configuration 6 (Read/Write)
Value after reset: 00
PC6
SXCL(1:0)
SCL(2:0)
Data Sheet
7
Select Transmit Clock Frequency on Port CLK2
Port CLK2 is the de-jittered DCO-X clock at a frequency of
00 = 1.544 MHz
01 = 3.088MHz
10 = 6.176 MHz
11 = 12.352 MHz
Select System Clock Frequency on Port CLK1
Port CLK1 is the de-jittered DCO-R clock at a frequency of
SIC2.SSC2=0:
000 = 8 kHz
001 = 2.048 MHz
010 = 4.096 MHz
011 = 8.192 MHz
100 = 16.384 MHz
101 to 111 = Not defined
SIC2.SSC2=1:
000 = 8 kHz
001 = 1.544 MHz
010 = 3.088 MHz
011 = 6.176 MHz
100 = 12.352 MHz
101 to 111 = Not defined
Note:If DCO-R is not active, no clock is output on pin CLK1
Note: If DCO-X is not used, no clock is output on pin CLK2
H
(SIC1.RBS(1:0)=11 and CMR1.RS1=0).
(SIC1.XBS(1:0)=00 and CMR1.DXJA=1; buffer bypass and
no jitter attenuation)
SXCL1
388
SXCL0
SCL2
SCL1
T1/J1 Registers
SCL0
FALC56 V1.2
0
PEB 2256
2002-08-27
(86)

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