peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 98
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peb2256
Manufacturer Part Number
peb2256
Description
E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB2256.pdf
(490 pages)
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• Clock adaption between system clock (SCLKX) and internally generated transmit
• Compensation of input wander and jitter.
• Frame alignment between system frame and transmit route frame
• Reporting and controlling of slips
Writing of received data from XDI is controlled by SCLKX/R and SYPX/XMFS in
combination with the programmed offset values for the transmit time slot/clock slot
counters. Reading of stored data is controlled by the clock generated by DCO-X circuitry
or the externally generated TCLK and the transmit framer. With the de-jittered clock data
is read from the transmit elastic buffer and are forwarded to the transmitter. Reporting
and controlling of slips is done according to the receive direction. Positive/negative slips
are reported in interrupt status bits ISR4.XSP and ISR4.XSN. If the transmit buffer is
bypassed data is directly transferred to the transmitter.
The following table gives an overview of the transmit buffer operating modes.
Table 22
SIC1.XBS(1:0)
00
11
01
10
4.4.5
The analog transmitter includes a programmable pulse shaper to satisfy the
requirements of ITU-T I.431. The amplitude and shape of the transmit pulses are
completely programmable by registers XPM(2:0).
The transmitter requires an external step up transformer to drive the line.
4.4.6
The transmit line monitor compares the transmit line current on XL1 and XL2 with an on-
chip transmit line current limiter. The monitor detects faults on the primary side of the
transformer indicated by a highly increased transmit line current (more than 120 mA for
at least 3 consecutive pulses sourced by V
by setting the transmit line driver XL1/2 into high-impedance state automatically (if
enabled by XPM2.DAXLT = 0). The current limiter checks the actual current value of
1)
Data Sheet
route clock (XCLK).
shorts between XL1 or XL2 and V
Programmable Pulse Shaper (E1)
Transmit Line Monitor (E1)
Transmit Buffer Operating Modes (E1)
Buffer Size
bypass
short buffer
1 frame
2 frames
DDX
are not detected
98
DDX
TS Offset
programming
enabled
enabled
enabled
enabled
1)
) and protects the device from damage
Functional Description E1
Slip performance
no
yes
yes
yes
FALC56 V1.2
PEB 2256
2002-08-27
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