peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 360

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

FALC56 V1.2
PEB 2256
T1/J1 Registers
Receive Frame Marker Offset (PC(4:1).RPC(2:0) = 001
)
B
Offset programming of the receive frame marker which is output on
multifunction port RFM. The receive frame marker can be activated
during any bit position of the entire frame and depends on the
selected system clock rate.
Calculation of the value X of the receive offset register RC(1:0)
depends on the bit position which should be marked at marker
position MP:
system clocking rate: modulo 2.048 MHz (SIC2.SSC2 = 0)
0 ≤ MP ≤ 2045:X = MP + 2
2046 ≤ MP ≤ 2047:X = MP - 2046)
e.g: 2.048 MHz: MP = 0 to 255; 4.096 MHz: MP = 0 to 511,
8.192 MHz: MP = 0 to 1023, 16.384 MHz: MP = 0 to 2047
system clocking rate: modulo 1.544 MHz (SIC2.SSC2 = 1)
0 ≤ MP ≤ 193 × (SC/SD) - 3:X = MP + 2 + 7 × SC/SD
193 × (SC/SD) -2 ≤ MP ≤ maximum delay:X = MP + 2 - 186 × SC/
SD
with maximum delay = 193 × SC/SD - 1
with SC = system clock defined by SIC1.SSC(1:0)+SIC2.SSC2
with SD = system data rate
Data Sheet
360
2002-08-27