peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 303

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peb2256

Manufacturer Part Number
peb2256
Description
E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet

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CRC Error Counter 3 (Read)
CEC3L
CEC3H
CE(15:0)
CE(7:2)
CE(1:0)
Data Sheet
CE15
CE7
7
7
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then reset automatically. The latched error
counter state should be read within the next second.
CRC Error Counter (detected at T Reference Point in S
GCR.ECMC = 0: If doubleframe format is selected, CEC3H/L has no
function. If CRC-multiframe mode is enabled, CEC3H/L works as S
bit error indication counter (16 bits) which counts the S
sequence 0010 and 0011in every received CRC submultiframe.
Incrementing the counter is only possible in the multiframe
synchronous state FRS0.LMFA = 0.
S
SA61 is received in frame 1 or 9 in every multiframe. The error
counter does not roll over.
During alarm simulation, the counter is incremented once per
submultiframe up to its saturation.
Multiframe Counter
GCR.ECMC = 1: This 6 bit counter increments with each multiframe
period in the asynchronous state FRS0.LFA/LMFA = 1.
During alarm simulation, the counter is incremented once per
multiframe up to its saturation.
Change of Frame Alignment Counter
GCR.ECMC = 1: This 2 bit counter increments with each detected
change of frame/multiframe alignment. The error counter does not roll
over.
During alarm simulation, the counter is incremented once per
multiframe up to its saturation.
Clearing and updating the counter is done according to bit
FMR1.ECM.
a
6-bit sequence: SA61, SA62, SA63, SA64 = 0010 or 0011 where
303
FALC56 V1.2
CE0
CE8
E1 Registers
0
0
PEB 2256
2002-08-27
a
6 -Bit)
(5A)
(5B)
a
6-bit
a
6-

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