peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 305

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Receive S
RSA6S
S_X
S_F
S_E
S_C
Data Sheet
a
6-Bit Status (Read)
7
Four consecutive received S
ETS300233 defined S
following “fixed” S
SA61, SA62, SA63, SA64 = 1000, 1010, 1100, 1110, 1111. All other
possible 4 bit combinations are grouped to status “X”.
A valid S
corresponding status bit in this register is set. Even if the detected
status is active for a short time the status bit remains active until this
register is read. Reading the register resets all pending status
information.
With any change of state of the S
status ISR0.SA6SC is generated.
During the basic frame asynchronous state updating of this register
and interrupt status ISR0.SA6SC is disabled. In multiframe format the
detection of the S
or
synchronous detection mode updating of register RSA6S is done in
the
asynchronous detection mode updating is independent to the
multiframe synchronous state.
Receive S
If none of the fixed S
Receive S
Receive S
the S
Receive S
Receive S
the S
Receive S
Receive S
the S
asynchronous
a
a
a
6-bit positions.
6-bit positions.
6bit positions.
multiframe
a
S_X
a
a
a
6-bit combination must occur three times in a row. The
a
a
a
a
6-bit status “1111” is detected for three times in a row in
6-bit status “1110” is detected for three times in a row in
6-bit status “1100” is detected for three times in a row in
6-Bit Status_X
6-Bit Status: "1111"
6-Bit Status: "1110"
6-Bit Status: "1100"
a
a
6-bit combinations can be done either synchronous
6-bit combinations:
S_F
synchronous
a
to
6-bit combinations are detected this bit is set.
a
305
6-bit combinations. The FALC56 detects the
the
S_E
submultiframe
a
6-bits are checked on the by
a
S_C
state
6-bit combinations an interrupt
S_A
(FRS0.LMFA = 0).
(FMR3.SA6SY).
FALC56 V1.2
S_8
E1 Registers
0
PEB 2256
2002-08-27
(61)
In
In