peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 249

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

JATT, RL
DRS
Pulse Count Detection Register (Read/Write)
Value after reset: 00
PCD
PCD(7:0)
Data Sheet
PCD7
7
Remote Loop Transmit Jitter Attenuator
00 = Normal operation. The remote loop transmit jitter attenuator is
01 = Remote loop active without remote loop transmit jitter
10 = not defined
11 = Remote loop and remote loop jitter attenuator active. Received
Note: JATT is only used to define the jitter attenuation during remote
Dual-Rail Select
0 =
1 =
Pulse Count Detection
A LOS alarm is detected if the incoming data stream has no
transitions for a programmable number T consecutive pulse
positions. The number T is programmable by the PCD register and
can be calculated as follows:
T = 16 × (N+1); with 0 ≤ N ≤ 255.
The maximum time is: 256 × 16 × 488 ns = 2 ms. Every detected
pulse resets the internal pulse counter. The counter is clocked with
the receive clock RCLK.
H
disabled. Transmit data bypasses the remote loop jitter
attenuator buffer.
attenuator enabled. Transmit data bypasses the remote loop
jitter attenuator buffer.
data from pins RL1/2 or RDIP/N or ROID is sent "jitter-free" on
ports XL1/2 or XDOP/N or XOID. The de-jittered clock is
generated by the DCO-X circuitry.
The ternary interface is selected. Multifunction ports RL1/2 and
XL1/2 become analog in/outputs.
The digital dual-rail interface is selected. Received data is
latched on multifunction ports RDIP/RDIN while transmit data is
output on pins XDOP/XDON.
loop operation. Jitter attenuation during normal operation is
not affected.
249
PCD0
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(38)