peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 36

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

•
Table 3
Pin
No.
73
79
76
Data Sheet
Pin
No.
C4
A2
B4
Pin Definitions - Clock Generation
Symbol
MCLK
SYNC
CLK1
Output (O)
Supply (S)
I
I + PU
O + PU
Input (I)
Function
Master Clock
A reference clock of better than ± 32 ppm
accuracy in the range of 1.02 to 20 MHz must
be provided on this pin . The FALC
internally derives all necessary clocks from this
master
(see registers GCM(6:1)).
Clock Synchronization of DCO-R
If a clock is detected on pin SYNC the
DCO-R circuitry of the FALC
to this 1.544/2.048 MHz clock (see LIM0.MAS,
CMR1.DCS and CMR2.DCF). Additionally, in
master mode the FALC
synchronize to an 8-kHz reference clock
(IPC.SSYF = 1). If not connected, an internal
pullup transistor ensures high input level.
System Clock of DCO-R
Output of the de-jittered system clock
generated by the DCO-R circuit. Frequency
selection is done by setting control bits in PC5/
6.
E1: 16.384 MHz, 8.192 MHz, 4.096 MHz,
2.048 MHz or 8 kHz
T1/J1: 16.384 MHz, 12.352 MHz, 8.192 MHz,
6.176 MHz, 4.096 MHz, 3.088 MHz, 2.048
MHz, 1.544 MHz or 8 kHz
After reset this output is inactive and internally
pulled high.
Note: If DCO-R is not active, no clock is output
36
on pin CLK1 (SIC1.RBS(1:0) = 11 and
CMR1.RS1 = 0).
®
56 is able to
®
Pin Descriptions
56 synchronizes
FALC56 V1.2
®
56
PEB 2256
2002-08-27