peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 400

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Global Clock Mode Register 5 (Read/Write)
Value after reset: 00
GCM5
MCLK_LOW
PLL_M(0:4)
Global Clock Mode Register 6 (Read/Write)
Value after reset: 00
GCM6
PLL_N(4:0)
Data Sheet
MCLK_
LOW
7
7
Master Clock Range Low
0 =
1 =
PLL Dividing Factor M
For details see calculation formulas below.
Note: Write operations to GCM5 initiate a PLL reset (see below).
PLL Dividing Factor N
Note: Write operations to GCM6 initiate a PLL reset (see below).
For details see calculation formulas below.
H
H
Master clock frequency divided by (PLL_M+1) is greater than or
equal 1.5 MHz
Master clock frequency divided by (PLL_M+1) is less than 1.5
MHz
PLL_M
PLL_N
4
4
400
PLL_M
PLL_N
3
3
PLL_M
PLL_N
2
2
PLL_M
PLL_N
1
1
T1/J1 Registers
PLL_M
PLL_N
FALC56 V1.2
0
0
0
0
PEB 2256
2002-08-27
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