peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 250

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Pulse Count Recovery (Read/Write)
Value after reset: 00
PCR
PCR(7:0)
Line Interface Mode 2 (Read/Write)
Value after reset: 20
LIM2
SLT(1:0)
Data Sheet
PCR7
7
7
Pulse Count Recovery
A LOS alarm is cleared if a pulse-density is detected in the received
bit stream. The number of pulses M which must occur in the
predefined PCD time interval is programmable by the PCR register
and can be calculated as follows:
M = N+1; with 0 ≤ N ≤ 255.
The time interval starts with the first detected pulse transition. With
every received pulse a counter is incremented and the actual counter
is compared to the contents of PCR register. If the pulse number is
higher or equal to the PCR value the LOS alarm is reset otherwise the
alarm stays active. In this case the next detected pulse transition
starts a new time interval.
Receive Slicer Threshold
00 = The receive slicer generates a mark (digital one) if the voltage
01 = The receive slicer generates a mark (digital one) if the voltage
10 = The receive slicer generates a mark (digital one) if the voltage
11 = The receive slicer generates a mark (digital one) if the voltage
H
H
at RL1/2 exceeds 55% of the peak amplitude.
at RL1/2 exceeds 67% of the peak amplitude (recommended in
some T1/J1 applications).
at RL1/2 exceeds 50% of the peak amplitude (default,
recommended in E1 mode).
at RL1/2 exceeds 45% of the peak amplitude.
SLT1
SLT0
250
SCF
ELT
PCR0
FALC56 V1.2
E1 Registers
0
0
PEB 2256
2002-08-27
(3A)
(39)