peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 50

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peb2256

Manufacturer Part Number
peb2256
Description
E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet

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3
3.1
The FALC
controlled by an external microprocessor or microcontroller.
The main interfaces are
• Receive and transmit line interface
• PCM system highway interface/H.100 bus
• Microprocessor interface
• Boundary scan interface
as well as several control lines for reset and clocking purpose.
The main internal functional blocks are
• Analog line receiver with equalizer network and clock/data recovery
• Analog line driver with programmable pulse shaper and line build out
• Central clock generation module
• Elastic buffers for receive and transmit direction
• Receive Framer, receive line decoding, alarm detection, PRBS and performance
• Transmit framer, receive line encoding, alarm and PRBS generation
• Receive jitter attenuator
• Transmit jitter attenuator
• Three HDLC controllers (one of them including SS7 and BOM support) and CAS
• Test functions (loop switching local - remote - payload - single channel)
• Register access interface
• Boundary scan control
Data Sheet
monitoring
signaling controller
®
Functional Description E1/T1/J1
Functional Overview
device contains analog and digital function blocks that are configured and
50
Functional Description E1/T1/J1
FALC56 V1.2
PEB 2256
2002-08-27

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