peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 428

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Interrupt Status Register 0 (Read)
Value after reset: 00
ISR0
All bits are reset when ISR0 is read.
If bit GCR.VIS is set, interrupt statuses in ISR0 are flagged although they are masked by
register IMR0. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
RME
RFS/BIV
ISF
RMB
Data Sheet
RME
7
RFS/BIV
Receive Message End - HDLC Channel 1
One complete message of length less than 32 bytes, or the last part
of a frame at least 32 bytes long is stored in the receive FIFO,
including the status byte.
The complete message length can be determined reading the RBCH,
RBCL registers, the number of bytes currently stored in RFIFO is
given by RBC(4:0). Additional information is available in the RSIS
register.
Receive Frame Start - HDLC Channel 1
This is an early receiver interrupt activated after the start of a valid
frame has been detected, i.e. after an address match (in operation
modes providing address recognition), or after the opening flag
(transparent mode 0) is detected, delayed by two bytes. After a RFS
interrupt, the contents of RAL1and RSIS.3-1 are valid and can be
read by the CPU.
BOM Frame Invalid - HDLC Channel 1
Only valid if CCR2.RBFE is set.
When the BOM receiver left the valid BOM status (detecting 7 out of
10 equal BOM frames) this interrupt is generated.
Incorrect Sync Format - HDLC Channel 1
The FALC56 did not detect eight consecutive ones within 32 bits in
BOM mode. Only valid if BOM receiver has been activated.
Receive Multiframe Begin
This bit is set with the beginning of a received multiframe of the
receive line timing.
H
ISF
RMB
428
RSC
CRC6
PDEN
T1/J1 Registers
FALC56 V1.2
RPF
0
PEB 2256
2002-08-27
(68)