cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 109

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
Table 4-3. E3 Clock Sources and Configuration Bits in SI-Bus Interface Mode
4.3.2
Table 4-4. DS1 Clock Sources and Configuration Bits in SI-Bus Interface Mode
29503-DSH-002-B
E3 Receive Framer Line Clock
(LINECLK)
E3 Transmit Framer Line
Clock (m13_clk_txlineo)
FOOTNOTE:
(1)
DS1 Receive Framer Line
Clock (RCKI)
DS1 Transmit Framer System
Clock (TSBCKI) and Line
Clocks (fr1_txclk_m13 and
fr1_clk_tx)
FOOTNOTE:
(1)
upl3txclkset[1:0] is located in the M13/E13 System Control register
TXE3_CLKSEL is located in the Clock Configuration register
XMTR_SEL_n[1:0] is located in Framer Control Registers 1 and 2
RCVR_SEL is located in Framer Control Register 1
FLOOP is located in the Rollback Configuration Register
Description
Description
DS1/E1 Clock and Data Configurations (SI-Bus Interface Mode)
The MUXes shown in
timing) and DS1/E1 modes (DS1 or E1).
settings for the DS1 and E1 modes, respectively.
CK_SRC[1:0] pins are set to 0
If the data path is unchannelized STS-1 or unchannelized DS3/E3, then the line and
system clocks listed in
framers can be disabled by setting RABORT in the Receiver Configuration register
(Section
34.368
34.368
(MHz)
(MHz)
Freq.
Freq.
1.544
1.544
8.3.2.5).
Mindspeed Technologies™
System or Looped
System
Looped
System or Looped
System
Looped
Preliminary Information
(Section
Timing Mode
Timing Mode
Figure 4-2
Tables 4-4
(Section
8.3.1).
(Section
×
0 or 0
are configured based on the Timing (system or loop
8.3.2.4).
(Section
and
(Section
8.8).
4-4
SONET Block
CLK_TXE3
LINECLK
×
M13/E13 Block
SONET Tributary
Mapper
CLK_TXDS1
Receive DS1 Clock
1.
Tables 4-4
Clock Source
8.3.1).
are not needed. Furthermore, the DS1/E1
8.4.1).
Source
Clock
Tables 4-4
and
Clock Sources and Clock Configurations
4-5
upl3txclkset[1:0] = 0 × 1
TXE3_CLKSEL = 0 × 1
upl3txclkset[1:0] = 0 × 0
TXE3_CLKSEL = Don't Care
RCVR_SEL = 0 × 0
FLOOP = 0 × 0
RCVR_SEL = 0 × 1
FLOOP = 0 × 0
XMTR_SEL_n[1:0] = 0 × 00
XMTR_SEL_n[1:0] = 0 × 2 or
0 × 3
and
list the configuration
Configuration Bits
Configuration Bits
4-4
assume the
—
(1)
(1)
4
-
5