cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 190

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

Register Description
0x73—Transmit Error Insert (TERROR)
Transmit error insertion capabilities are provided for system diagnostic, production test, and test equipment
applications. Writing a 1 to any TERROR bit injects a single occurrence of the respective error on the
transmitter output. Writing a 0 has no effect. Multiple transmit errors can be generated simultaneously. Injected
errors also affect data sent during a Framer Loopback [FLOOP; addr: 014].
TMERR
TBERR
TCOFA
TCERR
TFERR
0x74—Transmit Manual Sa-Byte/FEBE Configuration (TMAN)
8-60
RESERVED
INS_SA[8]
7
7
INS_SA[7]
Inject Multiframe Error—Injects a single Fs (T1) or MFAS (E1) bit error. TMERR performs a
logical inversion of the next multiframe bit transmitted. The processor can pace writing to
TMERR to control which MFAS bit is errored.
Inject PRBS Test Pattern Error—Injects a single PRBS error by logically inverting the next
PRBS generator output bit. The processor can pace writing to TBERR to create the desired bit
error ratio (up to 5
Inject Transmit COFA—Forces a 1-bit shift in the location of transmit frame alignment by
deleting 1 bit position from the transmit frame.
Inject CRC Error—Injects a single CRC6 (T1) or CRC4 (E1) bit error. TCERR performs a
logical inversion of the next CRC bit transmitted. The processor can pace writing to TCERR to
control which CRC bit is errored.
Inject Frame Bit Error—Injects a single Ft, FPS, or FAS bit error depending on the selected
transmit framer mode. TFERR performs a logical inversion of the next frame bit transmitted.
The processor can pace writing to TFERR, to control which frame bit is errored.
TMERR
6
6
Reserved bits should be written to 0.
0 = no effect
1 = inject multiframe error
0 = no effect
1 = inject PRBS error
Table 8-25. Transmit COFA Injection Options
0 = no effect
1 = inject CRC error
0 = no effect
1 = inject frame error
TCOFA
INS_SA[6]
TBERR
0
1
1
5
5
-3
if TBERR asserted 1/192 bits at every frame interrupt).
Mindspeed Technologies™
T1/E1N
INS_SA[5]
Reserved
X
0
1
Preliminary Information
4
4
No effect
Inhibit output of TS0 bit 1 for 1 frame
Inhibit output of F-bit for 1 frame
INS_SA[4]
TCOFA
3
3
Transmit COFA
FEBE_II
TCERR
2
2
TFERR
FEBE_I
1
1
CX29503 Data Sheet
29503-DSH-002-B
RESERVED
TFEBE
0
0