cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 177

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
0x46—Alarm/Error/Counter Latch Configuration (LATCH)
Unused bits should be written to 0.
STOP_CNT
LATCH_CNT
LATCH_ERR
29503-DSH-002-B
—
7
Stop Error Count during RLOF/RLOS/RAIS—If enabled, error count registers [addr: 050–
057] are suspended at their present values during any receive LOF (RLOF), LOS (RLOS), or
all 1s (RAIS) alarm condition. STOP_CNT does not affect the counting of test pattern errors
[BERR; addr: 058, 059] or alarm events [AERR; addr: 05A]. The occurrence of a red or AIS
Carrier Group Alarm (CGA) will inhibit further processing of all other performance
parameters (i.e., BER, errored seconds, SLIPS, etc.). However, a CGA caused by a yellow
alarm will not inhibit further alarm or performance monitoring.
Enable OneSec Latching of Counters—Determines the interval for which error counts remain
held in all count registers [addr: 050–057]. LATCH_CNT must be active in T1 mode whenever
automatic one-second performance report messaging [AUTO_PRM; addr: 0AA] is enabled.
When LATCH_CNT is inactive, the processor read of the LSB register reports the current LSB
error count, it latches the current MSB error count to the MSB register, and it clears the LSB.
Subsequently, reading the MSB register reports the current latched MSB error count and then
clears the MSB.
Enable OneSec Latching of Errors—Determines the interval for which latched active errors
are held in error interrupt [ISR5; addr: 006] and pattern interrupt [ISR0; addr: 00B] status.
—
6
0 = continue error count during alarms
1 = stop error count during alarms
Table 8-16. Latch Counter intervals
Table 8-17. Error Latching Options
NOTE:
IER
0
0
1
LATCH_CNT
—
5
0
1
Mindspeed Technologies™
LATCH_CNT being active during E1 mode prevents the processor from using RLOF
counter overflow [addr: 007] as a 128 ms MFAS time-out.
LATCH_ERR
0
1
X
Preliminary Information
—
4
Never
OneSec interval
Rising edge event
Rising edge event
Rising edge event
STOP_CNT
Count Latched
3
ISR Latched
LATCH_CNT
2
Until read clear
OneSec interval
LATCH_ERR
Until read clear
OneSec interval
Until read clear
Count Hold Time
1
ISR Hold Time
Register Description
LATCH_ALM
0
8
-
47