cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 65

• Manufacturer Part Number: cx29503
• Description: Cx29503 Broadband Access Multiplexer Data Sheet
• Manufacturer: Mindspeed Technologies

CX29503 Data Sheet
2.6.2.4
2.6.2.5
29503-DSH-002-B
DS3/E3 Mapping Function
The DS3/E3 Mapping function asynchronously maps a DS3/E3 signal into the
payload capacity of an L3 signal residing on the transmit-side, byte-wide data bus.
The DS3/E3 Mapping function implements a 96-bit mapping FIFO that is written at a
DS3/E3 rate and read at a gapped STS-1 rate. The FIFO is initialized at the half-full
position.
For the DS3 case, because there is 1 stuff opportunity per frame row, the read
sequence for every row is such that stuffing occurs in that row when the FIFO’s fill
level drops below the half-full level at the end of the preceding row. For the E3 case,
because there are 2 stuff opportunities every 3 frame rows, the read sequence for
every 3 rows is because that stuffing occurs in those 3 rows based on the following
after reading the previous three rows:
Because the write address in the DS3/E3 clock domain needs to be compared to the
read address in the STS-1 clock domain to determine the FIFO fill level, a
synchronization of these addresses needs to occur. A 2-bit counter in the DS3/E3
clock domain generates a 2/3 duty cycle signal (high 2 cycles, low 1 cycle) that is
sampled by the STS-1 clock to indicate that the write address has been incremented
by 3. An increment/decrement counter in the STS-1 clock domain then tracks the
FIFO fill level.
When overflows and underflows are detected, the overflow/underflow status is latched
and the FIFO is reset at the half-full position.
DS1/E1 Mapping Function
The DS1/E1 Mapping function asynchronously maps a DS1/E1 signal into the
payload capacity of an L1 signal residing on the transmit-side, byte-wide data bus.
The DS1/E1 Mapping function implements a 112-bit mapping FIFO that is written at
a DS1/E1 rate and read at a 19.44 MHz rate. The FIFO is initialized at the half-full
position. Because there are 2 stuff opportunities per VT/VC superframe, the read
sequence for every superframe is such that stuffing will occur in that superframe
based on the following at the end of the preceding superframe:
Because the write address in the DS1/E1 clock domain needs to be compared to the
read address in the 19.44 MHz clock domain to determine the FIFO fill level, a
synchronization of these addresses occurs. The DS1/E1 clock is sampled by the
19.44 MHz clock to indicate that the write address has incremented. An increment/
decrement counter in the 19.44 MHz clock domain then tracks the FIFO fill level.
When overflows and underflows are detected, the overflow/underflow status is latched
and the FIFO is reset at the half-full position.
0 bit stuffing: fill level has increased
1 bit stuffing: fill level has stayed constant
2 bit stuffing: fill level has decreased
0 bit stuffing: fill level has increased
1 bit stuffing: fill level has stayed constant
2 bit stuffing: fill level has decreased
Mindspeed Technologies™
Preliminary Information
Functional Description
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