cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 294
cx29503
Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
1.CX29503.pdf
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Register Description
8.5.2.2
8.5.2.3
8-164
Unchannelized STS-1/AU-3 or TUG-3 Mode
DS1 or E1 Mode
1.
2.
1.
2.
3.
4.
5.
Set the L3MAP[1:0] bits in the Level 3 Mapping Control register (0x6380) to
0x00 for unchannelized operation. Set the TUG3 bit to 0 for STS-1/AU-3
mapping or 1 for TUG-3 mapping.
At this point, the module is configured. Clear all status registers and interrupts to
remove any errors generated during the configuration process.
For DS1 or E1 Mode, set the L3MAP[1:0] bits in the Level 3 Mapping Control
register (0x6380) to 0x01 for tributary mapping. Set the TUG3 bit to 0 for STS-1/
AU-3 mapping or 1 for TUG-3 mapping.
For DS1, set registers GRPCFG1–GRPCFG7 (0x6388–0x638E) to 0x00.
For E1, set registers GRPCFG1–GRPCFG7 (0x6388–0x638E) to 0x10.
Set the VT registers TXL1MAPMIN (0x0E) to 0x38 to set the mapper FIFO
threshold.
Write a “0x00 → 0x01 → 0x00” sequence to the TXL1MAPRST registers (0x0F)
to reset the DS1/E1 mapper FIFOs.
At this point, the module is configured in DS1 or E1 mode. Clear all status
registers and interrupts to remove any errors generated during the configuration
process.
Mindspeed Technologies™
Preliminary Information
CX29503 Data Sheet
29503-DSH-002-B
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